HBM ClipX Bedienungsanleitung Seite 67

Example 1
Phase delay from input, e.g. 10 V, 20 mA or DC full/half bridge, to analog output
(10 V) with a Bessel filter at 1 kHz:
• A/D converter (ADC) plus filter: 690 μs.
Added to this is a jitter of up to 52 μs, as the A/D converter is not synchro-
nized with group 1. Group 1: 690 μs + 52 μs max.
• Analog output: 52 μs.
So the total phase delay is 742 ... 794 μs.
Group 2: Flags, Digital I/Os, calculated values, ClipX bus
from group 1,
group 3,
digital input
or ClipX bus
1)
Changes in digital flags are analyzed in the following order: Zeroing, taring, clear
zero value, clear tare value, reset limit value switch, reset peak values, hold held
values, clear hold values.
2) Asynchronous transfer of the values on the ClipX bus is complete after max. 1 ms, i.e on
the next cycle.
Fig. 32: Maximum phase delay for group 2: 1 ms
Example 2
Phase delay from input (see group 1) to a digital output with a Bessel filter at
1 kHz, limit switch at half the step height.
• A/D converter (ADC) plus filter: 690 μs.
Added to this is a jitter of up to 52 μs, as the A/D converter is not synchro-
nized with group 1. Group 1: 690 μs +60;μs max.
ClipX
max. 1 ms
Computed Digital flags
channels (I/O flags)
A04643_04_X00_03 HBM: public
Electrical connections, LEDs
+0,25 ms
Digital
outputs
1)
+1 ms max.
ClipX bus:
Start transfer
to group 4
2)
65