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Group 2: Flags, Digital I/Os, calculated values, ClipX bus
from group 1,
group 3,
digital input
or ClipX bus
1)
Changes in digital flags are analyzed in the following order: Zeroing, taring, clear
zero value, clear tare value, reset limit value switch, reset peak values, hold held
values, clear hold values.
2)
Asynchronous transfer of the values on the ClipX bus is complete after max. 1 ms, i.e on
the next cycle.
Abb. 37: Maximum phase delay for group 2: 1 ms
Example 2
Phase delay from input (see group 1) to a digital output with a Bessel filter at 1 kHz, limit
switch at half the step height.
•
A/D converter (ADC) plus filter: 690 μs.
Added to this is a jitter of up to 52 μs, as the A/D converter is not synchronized with
group 1.
Group 1: 690 μs + 52 μs max.
•
Group 2: 1 ms.
•
Digital output: max. 250 μs response time.
In the best case, a value is available at the start of the analysis in group 2 and can be
outputted directly at the digital output for example. So the total phase delay is 940 ...
1992 μs.
Example 3
Phase delay of a value from the ClipX bus via a limit switch to a digital output.
•
Group 2: 1 ms max.
•
Digital output: 250 μs response time.
In the best case, a value is available at the start of the analysis in group 2 and can be out-
putted directly at the digital output. However, you must add the phase delay in the device
ClipX
Electrical connections, LEDs
max. 1 ms
Computed
Digital flags
channels
(I/O flags)
+0,25 ms
Digital
outputs
1)
+1 ms max.
ClipX bus:
Start transfer
to group 4
2)
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