HBM ClipX Bedienungsanleitung Seite 111

Bit Explanation for bit set
0
Fill trigger mode for continuous filling
values per second. Recording starts immediately with the specified number
of values per second, taking into account any differential conditions.
1
Fill trigger mode for status-controlled filling
the digital flags determines the filling, see
status)" on page
of the bits is set and an active difference condition is fulfilled.
2
Fill trigger mode for edge-controlled filling
digital flags determines the filling, see
status)" on page
sible signal sources if one of the bits changes and an active differential con-
dition is fulfilled. With this function, in contrast to the other mode of
operation, the change of only one bit from High to Low or from Low to High
several
with
8 Records 1 measured value each from all 6 possible signal sources immedi-
ately into the FIFO, even if the respective trigger condition is not fulfilled. The
value must be recorded together with one of the fill trigger modus status- or
edge-controlled filling, e.g. as 0x0102 or 0x0104. The current date and time
are stored as the start time and the time channel is set to 0. You should stop
a still running recording before the command and read out the FIFO memory,
since the FIFO memory is not deleted. The bit is deleted after execution.
12 Overflow of the FIFO. The bit is cleared when writing the control flags, RO.
13 Ethernet error The bit is cleared when writing the control flags, RO.
1)
Only one of the various fill modes can be active at any given time, meaning you can only
ever set one of these bits.
Structure of the FIFO header data for the RMB command
See also „Accessing via standard Ethernet and object dictionary" on page
The first 32 bytes (header data) are 8 values with 4 bytes each. The byte order Little
Endian is used, i.e. the first byte is the LSB (Least Significant Byte).
ClipX
Operation via Ethernet/OPC UA/PPMP
157. Filling is active if the result is not 0, i.e. if at least one
157. 1 measured value is recorded from each of the 6 pos-
already active bits (High) is also recognized as a trigger.
1)
of the FIFO with the set number of
1)
of the FIFO. The bit mask of
„Digital flags: List of I/O flags (I/O
1)
of the FIFO. The bit mask of the
„Digital flags: List of I/O flags (I/O
103.
109