Sharp SF-2052 Serviceanleitung Seite 227

B. Solenoid drive circuit
[a] Paper feed solenoid (DFSOL), reverse solenoid (DRSOL) drive circuit
This circuit drives the weight plate which presses the bundle of originals on the tray, the paper feed solenoid which drives the paper feed section
shutter, and the reverse solenoid which drives the reverse guide to lead an original to the reverse path when reversing. The basic composition is the
same. The drive signal (ON at HIGH) from the gate array is inputted to the gate of FET (Q14, Q15).
The ON duty of the drive signal can be varied from 0 to 100% (255 steps). The frequency, however, is 20kHz.
G/A
(IC7)
PWM2
PWM1
C. Other circuit
[a] EEPROM (IC3) circuit
This circuit serves as a memory to save the sensitivity data of the reflection type sensors, the adjustment values such as the original set position on
the original table, and the counter values such as the number of originals passed. Data communication with the CPU (IC11) is performed with the
3-wire serial interface.
The saved data are maintained even when the power is turned off.
IC3 1 pin is the chip select pin, which is driven to HIGH when data communication is performed.
2 pin is the serial lock pin, and the serial data are transmitted in synchronization with the clock inputted to this pin.
3 pin is the input pin of serial data from the CPU. 4 pin is the output pin of serial data from IC3.
D1, R50, and C1 form a circuit which keeps the power of IC3 at a constant level even when a sudden power drop occurs during data writing.
TP28
R88
15
1.0K
TP36
R82
14
1.0K
+5V
D1
E2ROM+5V
R49
R50
10
100K
IC3
C1
100µ F
6
ORG
7
NU
93LC46TSN
+24V
D8
SS14
Q14
2SK1726
PGND
FD+24V
D7
SS14
Q15
2SK1282-Z
PGND
Solenoid drive circuit
+5V
SB02-030
D3
4 R4 22K
DO
1 R3 22K
*CS
2 R2 22K
CLK
3 22K
R1
DI
EEPROM circuit
12 – 24
173981-7
4
+24V CN8-4
5
DRSOL CN8-5
DF1B-9P-2^5DSA
4
+24V
CN5-4
3
DFSOL CN5-3
CPU
(IC11)
R24
60
P74/ANI4
10K
51
P14
52
P15
50
P13
R8 R42 R41
10K 10K 10K
Reverse
DRSOL
solenoid
Paper feed
DFSOL
solenoid