Sharp SF-2052 Serviceanleitung Seite 217

(3) ROM
1
General
A. Program ROM (IC410) (27C512)
B. Data ROM (IC411) (27C010)
C. G ROM (IC414) For storing graphic data. (27C04)
D. C.G ROM (IC501) For storing character data. (Mask ROM)
2
Pin arrangment (IC410/IC411)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
ROM pin signals (IC410/411)
PIN No. IN/OUT Signal name
1 IN
2 IN
3
( IN
10
11
( OUT
13
14 —
15
(
OUT
19
20 IN
21
IN
22
23 IN
24 IN
25 IN
26 IN
27 IN
28 —
28
27
26
25
24
23
22
27C010
21
20
19
18
17
16
15
Description
A15 Address signal
A12 Address signal
A7 Address signal
(
A0
D0 Data signal
(
D2
GND GND (0V)
D3 Data signal
(
D7
ROM chip enable signal.
CE When LOW, ROM data
output enabled.
Address signal
A10 Data output enable signal.
OD When LOW, ROM data
arte sent to CPU.
A11 Address signal
A9 Address signal
A8 Address signal
A13 Address signal
A14 Address signal
5V Power source
4
Pin arrangement (IC414)
5
ROM pin signals (IC414)
Pin No. IN/OUT
1 IN
2
3
4
IN
5
(
12
13
14 OUT
15
16 —
17
( OUT
21
22 IN
23 IN
24 IN
25
26
27 IN
28
29
30 IN
31 IN
32 IN
(4) Operation
1
The CPU receives image data from the main body. (Key data and
LED data are also transmitted.)
2
The received image data (corresponding to DATA-ROM address)
are used to read character data (corresponding to CG-ROM ad-
dress) and graphic data (corresponding to G-ROM address) in the
DATA-ROM.
CG-ROM --- Standard Kanji character storing ROM
G-ROM ----- Graphic data storing ROM
3
The upper address and the lower address of CG-ROM and G-
ROM corresponding to characters and graphic data respectively
are written into two V-RAMs (image areas).
4
The LCD controller outputs the specified address of character and
graphic data to be displayed. The CG-ROM outputs the data cor-
responding to the specified address through the data bus to the
display unit.
5
The image data are transferred to the LCD unit.
12 – 14
1 32
27C04
16 17
Signal name Functions and operations
Vpp 5VS(+5V)
A16
A15 Address signal
A12
A7
(
A0
D0 Data signal
D1
D2
GND GND (0V)
D3 Data signal
(
D7
Chip select signal. When
PROMCS LOW (0V), ROM1 (IC530) is
selected.
A10 Address signal
When LOW (0V), ROM1
RD (IC530) data is read by the
CPU (IC514).
A11 Address signal
A9
A8
A13
A14
A17 Address signal
Program enable input.
PGM When LOW (0V), program
write enable.
Vcc 5VS(+5V)