Sharp SF-2052 Serviceanleitung Seite 206

(1) CPU (IC2) Signal list
Pin No. Signal name
1
THVG
2
SHVG
3 BIAS
4 PPD3
5
DWMA
6
DWMB
7 DWMA
8 DWMB
9
+5V (C)
F
FWS
G RRCin
H BLTin
I
-PFCin
J
DBMA
K DBMB
L DBMA
M DBMB
N TxD_OP
O RxD_OP
P
TxD_MIR
Q RxD_MIR
R TxD_SOT
S RxD_SOT
T
TxD_RIC
U RxD_RIC
V GND2
W SA
X
SB
Y
SC
Z CLinh
[ BLCLOCK
\
BLDATA
] BLLATCH
^
BLBEO
_
GND2
' D0
a D1
b
D2
c
D3
d D4
e D5
f
D6
g
D7
h +5V (C)
i A0
j A1
k
A2
l A3
m
A4
n A5
o A6
p A7
q
GND2
r A8
s A9
t A10
Port In/Out
P90/PW3/IOF10 OUT
P91/PW4/IOF11 OUT
P92/PW5/IOF12
OUT
P93/IOF13
OUT
P94/IOF14 OUT
P95/IOF15 OUT
P96/IOF16 OUT
P97/IOF17
OUT
Vcc IN
P100/IOF20
IN
P101/IOF21
IN
P102/IOF22
IN
P103/IOF23 IN
P104/IOF24
OUT
P105/IOF25
OUT
P106/IOF26
OUT
P107/IOF27 OUT
P80/IOF00
OUT
P81/IOF01
IN
P82/IOF02 OUT
P83/IOF03 IN
P84/IOF04
OUT
P85/IOF05
IN
P86/IOF06 OUT
P87/IOF07
IN
Vss
IN
P120/D8
OUT
P121/D9
OUT
P122/D10
OUT
P123/D11
OUT
P124/D12
OUT
P125/D13
OUT
P126/D14
OUT
P127/D15 OUT
Vss IN
D0 IN/OUT
D1
IN/OUT
D2 IN/OUT
D3 IN/OUT
D4 IN/OUT
D5
IN/OUT
D6 IN/OUT
D7
IN/OUT
Vcc
IN
A0
OUT
A1
OUT
A2
OUT
A3
OUT
A4 OUT
A5 OUT
A6
OUT
A7
OUT
Vss IN
A8 OUT
A9
OUT
A10
OUT
H/L
"H" Transfer charger output
"H" Separation charger output
Developer bias output
"H"
PPD3 ON detection
H
— Duplex alignment plate stepping motor phase A
— Duplex alignment plate stepping motor phase B
— Duplex alignment plate stepping motor phase A
Duplex alignment plate stepping motor phase B
—
— CPU power (+5V)
"H" ↑
FW zero-cross signal input
Resist roller clutch timing trigger
"H"
"L" ↓
BL timing trigger
"H" PFCin signal monitor
Duplex rear plate stepping motor phase A
—
Duplex rear plate stepping motor phase B
—
Duplex rear plate stepping motor phase A
—
— Duplex rear plate stepping motor phase B
Serial out (for operation panel)
"L" START
Serial in (for operation panel)
"L" START
"L" START Serial out (for mirror control)
"L" START Serial in (for mirror control)
Serial out (for sorter)
"L" START
Serial in (for sorter)
"L" START
"L" START Serial out (for RIC)
Serial in (for RIC)
"L" START
CPU power (0V), signal GND
—
Strobe output A
H/L
Strobe output B
H/L
Strobe output C
H/L
Copy lamp ON inhibit
"H"
BL clock output
H/L
BL data output
H/L
BL latch output
H/L
"H" BL enable (ON/OFF) control
— CPU power (0V), signal GND
H/L Data bus 0
Date bus 1
H/L
H/L Data bus 2
H/L Data bus 3
H/L Date bus 4
Data bus 5
H/L
H/L Data bus 6
Data bus 7
H/L
CPU power (+5V)
—
Address bus A0
H/L
Address bus A1
H/L
Address bus A2
H/L
Address bus A3
H/L
H/L Address bus A4
H/L Address bus A5
Address bus A6
H/L
Address bus A7
H/L
— CPU power (0V), signal GND
H/L Address bus A8
Address bus A9
H/L
Address bus A10
H/L
12 – 3
Description