Nanotec NP5-20 Technisches Handbuch Seite 31

4 Hardware-Installation
Anschlussbelegung NP5 PHY Device Configuration
+3.3V
PHY 0 Device Configuration
PHYAD0_NANDTREE(0)
R26 1k
NWAYEN(0)
R27 1k
RX_CLK_B-CAST_OFF(0)-S2
R28 1k
LINK_MII_SPEED(0)-S2
R29 1k
RX_D3_PHYAD0(0)-S2
R30 4k7
RX_D2_PHYAD1(0)-S2
R31 4k7
RX_D1_PHYAD2(0)-S2
R32 4k7
RX_D0_DUPLEX(0)-S2
R33 4k7
RX_ERR_ISO(0)-S2
R34 4k7
RX_DV_CONFIG2(0)-S2
R35 4k7
MII_CONFIG1(0)
R36 4k7
MII_CONFIG0(0)
R37 4k7
+3.3V
PHY 0
IC3
21
INTRP_NAND_TREE
PHYAD0_NANDTREE(0)
12
MI_CLK/LINKPOL-S2 MDC
11
MDIO
MI_DATA-S2
29
CRS_CONFIG1
MII_CONFIG1(0)
28
COL_CONFIG0
MII_CONFIG0(0)
20
RXER_ISO
RX_ERR_ISO(0)-S2
19
RXC_B-CAST_OFF
RX_CLK_B-CAST_OFF(0)-S2
18
RXDV_CONFIG2
RX_DV_CONFIG2(0)-S2
13
RX_D3_PHYAD0(0)-S2 RXD3_PHYAD0
14
RXD2_PHYAD1
RX_D2_PHYAD1(0)-S2
15
RXD1_PHYAD2
RX_D1_PHYAD2(0)-S2
16
RXD0_DUPLEX
RX_D0_DUPLEX(0)-S2
22
TXC
23
TXEN
TX_ENA(0)-S2
27
TX_D3(0)/C25_SHI[1]-S2 TXD3
26
TXD2
TX_D2(0)/C25_SHI[0]-S2
25
TXD1
TX_D1(0)-S2
24
TXD0
TX_D0(0)/C25_ENA-S2
31
LINK_MII_SPEED(0)-S2 LED1_SPEED
30
LED0_NWAYEN
NWAYEN(0)
KSZ8081MNXI
PHY 1
IC4
21
INTRP_NAND_TREE
PHYAD0_NANDTREE(1)
12
MDC
MI_CLK/LINKPOL-S2
11
MDIO
MI_DATA-S2
29
MII_CONFIG1(1) CRS_CONFIG1
28
COL_CONFIG0
MII_CONFIG0(1)
20
RXER_ISO
RX_ERR_ISO(1)-S2
19
RXC_B-CAST_OFF
RX_CLK_B-CAST_OFF(1)-S2
18
RX_DV_CONFIG2(1)-S2 RXDV_CONFIG2
13
RXD3_PHYAD0
RX_D3_PHYAD0(1)-S2
14
RXD2_PHYAD1
RX_D2_PHYAD1(1)-S2
15
RX_D1_PHYAD2(1)-S2 RXD1_PHYAD2
16
RXD0_DUPLEX
RX_D0_DUPLEX(1)-S2
22
TXC
23
TXEN
TX_ENA(1)-S2
27
TXD3
TX_D3(1)/P_MODE[1]-S2
26
TXD2
TX_D2(1)/P_MODE[0]-S2
25
TXD1
TX_D1(1)-S2
24
TXD0
TX_D0(1)/TRANS_MODE_ENA-S2
31
LED1_SPEED
LINK_MII_SPEED(1)-S2
30
LED0_NWAYEN
NWAYEN(1)
KSZ8081MNXI
Version: 1.5.0 / FIR-v2213
+3.3V
PHYAD0_NANDTREE(1)
R43 1k
NWAYEN(1)
R44 1k
RX_CLK_B-CAST_OFF(1)-S2
R45 1k
LINK_MII_SPEED(1)-S2
R46 1k
RX_D3_PHYAD0(1)-S2
R47 4k7
RX_D2_PHYAD1(1)-S2
R48 4k7
RX_D1_PHYAD2(1)-S2
R49 4k7
RX_D0_DUPLEX(1)-S2
R50 4k7
RX_ERR_ISO(1)-S2
R51 4k7
RX_DV_CONFIG2(1)-S2
R52 4k7
MII_CONFIG1(1)
R53 4k7
MII_CONFIG0(1)
R54 4k7
+3.3V +3.3V
2
VDD_1.2
3
VDDA_3.3
17
VDD_IO
G
GND
1
GND
32
RST
PHY_RESET-S2
10
6k49 R39
REXT
9
XI CLK_25MHZ-S2
8
XO
7
TX+
6
TX-
5
RX+
4
RX-
+3.3V +3.3V
2
VDD_1.2
3
VDDA_3.3
17
VDD_IO
G
GND
1
GND
32
RST PHY_RESET-S2
10 6k49 R40
REXT
9
XI
CLK_25MHZ-S2
8
XO
7
TX+
6
TX-
5
RX+
4
RX-
Nanotec Electronic GmbH
Kapellenstr. 6
D-85622 Feldkirchen b. München
PHY 1 Device Configuration
+3.3V
X2
1
2
PHY0_LINKACT_LED-S2
3
4
5
C27 100n/16V
6
7
8
C28 100n/16V
9
PHY0_YELLOW_LED-S2
10
G1
G2
RJ45_WE_7498011211
+3.3V
X3
1
2
PHY1_LINKACT_LED-S2
3
4
5
C29 100n/16V
6
7
8
C30 100n/16V
9
PHY1_YELLOW_LED-S2
10
G1
G2
RJ45_WE_7498011211
NP5_ETHERCAT
06.06.2017 16:59
NP5_REF_ETHERCAT (003) 3/3
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