Introduction; Equipment Required; Adjustment And Test Point Locations; Self Test - Tektronix DC 5010 Anleitung

Introduction
The following information is intended to aid in the diagno-
sis and repair of a malfunctioning instrument. With power-on
Self Test, signature analysis checks, and other
troubleshooting data, the qualified service personnel will be
able to verify proper operation or detect malfunction in this
instrument.
Not all of the instrument faults may be isolated by this
information or indicated by the instrument's built-in self test
features. The service personnel should then refer to the
Theory of Operation section, in this manual for a better un-
derstanding of the circuit details.
Equipment Required
The recommended diagnostic tests require the following
equipment or equivalent.
Data analyzer.
Digital counter.
Digital multimeter.
TEKTRONIX type SA 501 or type 308
Data Analyzer (for signature analysis)
TEKTRONIX type DC 503A (for time-
base frequency checks)
TEKTRONIX type DM 501A (for
checking power supplies)
Also refer to the equipment list in the Calibration section
of this manual for suggestions on oscilloscope systems,
probes, adapters, terminations and other equipment that
may be useful for troubleshooting purposes.
Adjustment and Test Point Locations
When locating adjustable components and test points,
refer to the Adjustment and Setups Location in the pullout
pages of this manual.
Self Test
The DC 501 0 has three modes of self test. The automatic
test sequence at power on, the TEST function selected by
the front panel FUNCTION switch and the TEST function via
the GPIB.
The automatic test sequence at power-on (Power On
Self Test) is initiated each time the power is applied to the
instrument. The microprocessor sequences through special
data patterns to test the operation of the circuits in the in-
strument. At power-on, after the microprocessor reset line
has been released, the following tests are performed:
1. The display (time slot generator, schematic 10) is
reset to the most significant digit (digit to extreme left) and a
0 readout is displayed.
2. The RAM is tested by writing a known bit pattern into
the RAM and reading it back. Each byte in the RAM is veri-
fied. If any byte does not verify, the RAM test error code is
displayed on the front panel and the test sequence stops.
The patterns written are FF, AA, 55, 00 (hexidecimal) in suc-
cession leaving the RAM cleared when the test is finished. If
this test is not successfully completed, the proper error
code is displayed and the self test sequence stops.
3. The ROM's are checked for both placement and also
proper checksums. If any of these tests fail, the power on
self test sequence is stopped and the proper error code is
displayed.
4. Next, the automatic test sequence sets the instru-
ment gating to the RATIO B/A function.
5. The serial I/O data loop is checked next, by writing
-.
out a data pattern to the serial-to-parallel shift registers. The
data pattern is read back through the parallel-to-serial shift
registers. If the data are correct, the power-on sequence
continues. If the data are not correct, the error code for this
test is displayed and the test sequence stops. This test
checks the shift registers and the data path, including the
serial clock but does not check the input or output stages of
the shift registers or the latch control lines. Troubleshooting
of the serial I/O loop is best accomplished using signature
analysis.
6. The next test is the counter integrity test. This test
first resets the instrument's Channel A and Channel B accu-
mulators by pulsing the MR (master reset) line. It then
checks each of the tested counter stages to verify that all
bits are reset. If any bits are not reset, the proper error code
is displayed and the test sequence stops. Next, the
signal, (schematic 3) is asserted. The instrument theninputs
counts to the accumulators. These counts are generated by
changing the trigger levels for both Channel A and Channel
B using the' D/A converters. The D/A converter level
changes (cycles) from its current setting to +2.0 V then to
-2.0 V and back to +2.0 V. This cycle represents one
count if the Channel A and Channel B input voltages are
within this voltage range and the ARM signal, (schematic 6)
is in the high state.
After each cycle or set of cycles, the accumulators are
read and checked to see if the proper count has been