Tektronix DC 5010 Anleitung Seite 281

REAR INTERFACE CONNECTORS
--
Introduction
Refer to Fig. 5-6 for the following.
I
OUTPUT O R
1
NPUT
A slot between pins 21 and 22 on the rear connector
identifies this instrument as a member of the TM 5000
counter family. Insert a barrier in the corresponding position
of the power module jack to prevent noncompatible plug-ins
from being used in that compartment. Consult the power
module manual for further information.
28
P I N
B
Functions Available at Right Rear Interface
Connector (P 1 600)
I
23
22
21
Pin 14A.
Pin 148.
Pin 15A.
Pin 158.
Pin 26A.
P I N
A
28
External Clock Input-This input allows an exter-
nal 1,5, or 10 MHz frequency standard to be used
in place of the internal timebase. The input is ac
coupled and has a 1 kQ input resistance. The
peak-to-peak input voltage required is a0.5 V.
OUTPUT O R
INPUT
ARMING INPUT
GROUND
BARRIER
SLOT
GROUND
F l
23
,
22
21
Prescale-When this available line is held low, the
counter automatically adjusts the displayed an-
swer for use with a divide-by-16 prescaler in
FREQ A, PERIOD A, RATIO BIA, and TOTALIZE
A modes
(GI
TTL load).
I
PRESCALE
1
14
1
1
:l
1
BASE LEAO OF
1
PNP SERIES PASS
EMITTER LEAD OF
PNP SERIES PASS
10 MHz Clock Out Ground-This terminal is the
ground return for the clock input-output signals.
I t
f26V COMMON 9
COLLECTOR LEAO OF EMITTER LEAD OF
NPN SERIES PASS
10 MHz Clock Out-This available output line will
drive one TTL load. This line is not intended to
drive large capacitance loads and cable length
should be kept to a minimum.
TM 5000
BARRIER
SLOT
Reset Input-When this line is set low, the current
pulse width of approximately 10 ms.) When not used, the
Fig. 5-6. Right rear interface connector assignments.
line is in the high state.
measurement process is aborted for all selected functions
and causes all digits in the display to read 8.8.8.8.8.8.8.8.8.
All eight annunciators (and push buttons)are also illuminat-
ed. When this line is set high, a new measurement process
prevented from making a measurement until the
input goes to a TTL high state. When this input is
routed to the rear interface it is dc coupled to the
front panel arm signal. (' H a 2.4 V, "L ~ 0 . 4 V
approximately 2 TTL loads).
Pin 27A. Arming Input-This terminal is normally at a TTL
high level. When pulled to a TTL low state with a
1-
TTL signal or transistor collector, the counter is
is initiated for the selected FUNCTION and operating condi-
3897-1 8
tions. (CMOS 'IL ~ 1 . 5 V and ' I H a3.5 V with a minimum
*8v COMMON
+8V DC
3
2
1
REAR
VIEW
OF
PLUG-IN
3
'
2
1
*8v COMMON
*8V DC