Tektronix DC 5010 Anleitung Seite 242

Theory of Operation-DC 50 1 0
Time Base,
320 MHz PLL, and Noise Generator Pusbuttons and LED9s/Display
This block contains the 10 MHz crystal controlled time
base, a 320 MHz PLL (phase-locked loop) and a pseudo-
random noise generator that is activated for time interval
averaging measurements.
The 320 MHz PLL circuit contains a frequency and phase
comparator, a filter circuit, a Varactor diode for 320 MHz
tuning, and a feedback loop consisting of a fast divide-by-4
section followed by a divide-by-80 section.
The key element in this functional block is a ten-state
-
decade counter that provides the time slot decoding for -
scanning the front panel pushbuttons and other controls.
The counter also provides the multiplexing functions for the
seven-segment LED display and annunciators. Information
is presented to the display by latching six bits of data from
the microprocessor parallel data bus. Four bits of the
latched data are then decoded from binary coded decimal to
seven-segment information. The remaining two bits are
used to drive the annunciators and decimal points.
CH A and CH B Count Chains
The display consists of nine seven-segment LEDs,
The Channel A signal is divided or counted by four ECL
binary stages, five LS TTL binary stages, and then by four
binary stages in a single CMOS counter. The CH A SLOW
output from the CMOS counter is then applied to a micro-
processor peripheral device on schematic 9, where the sig-
nal is counted by another 16 binary stages internal to that
device.
The CH B Accumulator is similar to the CH A Accumula-
tor with four ECL binary stages, five LS TTL binary stages,
followed by 15 binary stages in two CMOS counters. The
CH B SLOW signal is also applied to the microprocessor
peripheral device on schematic 9. Each accumulator circuit
has ECL to TTL or ECL to CMOS translator circuits where
required.
The outputs of these counters are applied to the parallel
inputs of five parallel-to-serial shift registers (two for CH A
and three for CH B). To obtain the binary count accumulated
in these counters, the microprocessor asserts the Serial
Read Latch Line at least once for every measurement
interval.
Processor and Display Drivers
The microprocessor located on the GPlB board controls
the measurement gate interval, generates the relay strobe
signal, and by using address decoding circuits enables the
shift registers, display strobe circuits, and the data buffer for
the front panel button sensing. This functional block has a
microprocessor peripheral device containing a 128
x
8 stat-
ic RAM, a 2048
x
8 ROM, a programmable counter, an 8-
bit serial data channel, bidirectional data lines, and interrupt
inputs. Additional program memory space is provided by a
4096
x
8 ROM and a 256
x
8 RAM.
annunicators, and the LEDs of the lighted pushbuttons. The
time slot lines generated by a ten-state decade counter
drives the common cathodes of the seven-segment LEDs
and scans the buttons and annunciators. The anodes of the
seven-segment LEDs are connected to a buffer circuit
through current limiting resistors.
Power Supplies
The instrument draws power from both of its power mod-
ule connectors to derive its four primary supplies: +5V and
+12 V on the Auxiliary board and another +5 V and a
-
12 V supply on the Digital board. Each supply is current
limited and individually fused, and all four are referenced to a
single precision 2.5 V reference IC. Several secondary sup-
, ,
plies include +2.7 V for the ECL terminator, a
+
18 V three-
terminal regulator chip (in option 01 timebase only), a -5 V
supply derived from the
-
12 V, a 2.5 V supply to drive the
reference IC, and several isolated versions of +5 V, sepa-
rated by L-C filters.
GPlB Interface
The GPlB consists mainly of a microprocessor, two
ROM's, one RAM, and a GPlB controller chip. An address
switch is also available, which sets the listen and talk ad-
dresses for the DC 501 0. In the DC 5010, the GPlB board
connects to the digital board and is used to communicate
with the IEEE-488 Digital Interface.
The microprocessor uses a serial data loop, an 8-bit par-
allel data bus, and a 16-bit address bus to communicate
with the instrument functions. The microprocessor fetches
instructions from memory via the parallel data path, de-
codes the desired operation, and executes the instruction.
The activities of the microprocessor occur in cycles generat-
ed by its own 1 MHz system clock.
REV OCT 1981