Tektronix DC 5010 Anleitung Seite 250

Theory of Operation-DC 501 0
the
GPlB
board
-
Diagram
12),
controls the internal oper-
ations of the DC 501 0. The microprocessor recognizes, ac-
cepts, and decodes commands (keypushes and control
setting) from the front panel logic circuits (Diagram 10) and
sets the operating parameters in response to these
commands.
lntegrated circuit U1410 contains a random access mem-
ory (RAM) space that provides a maximum of 128 locations
(addresses) which the microprocessor uses to temporarily
store 8-bit data bytes. The data are not permanent and will
be lost whenever the instrument power is turned off. When
power is first applied, the RAM data occur as random bits
and are therefore meaningless. During instrument operation,
the microprocessor writes data into the RAM at various ad-
dresses for later recall and use.
The instructions for the microprocessor concerning GPlB
operation are stored in the EPROMS U1102 and U1201 (lo-
cated on the GPlB board). These IC's each contain 4 k
bytes memory. The instructions (firmware) concerning man-
ual operation of the DC 501 0 are stored in EPROM U1610
(also a 4 k byte memory) and in the ROM section of U1410
(a 2 k byte memory). The other RAM is located in U1311
(located on Digital board) and U1210 (located on the GPlB
board).
System Clock
The microprocessor, U1301, contains a single phase in-
ternal clock generator at pins 37 and 39, whose 1 ps period
(approximately) is controlled by inverter U1312D and the rc
feedback network consisting of R1301 and C1302. The ac-
tivity of U1301, when it is reading data from or writing data
to a memory device, occurs in machine (U1301) cycles.
Since no critical system timing relies on the microprocessor
clock, a crystal is not needed.
Power Up Reset Cycle
When the instrument is powered up, comparator
U1102D (and associated components) operates as a delay1
comparator circuit to provide a pulse to reset the micro-
processor to its reset vector address location.
Pin 14 of U1102D is held low for approximately 1.5 sec-
onds (to allow all supplies to come up to 0peratin.g status in
the TM 5000-Series power modules). During this time all of
the internal registers of U1410 (except the 16-bit counter
and serial shift register) are cleared to logic zero. This action
places all of the bidirectional inputloutput lines of U1410 in
the input state and disables the internal shift register, Dis-
play lnterrupt Clock input (pin 37), and the interrupt output
(pin 4). Also, during the low level period of the micro-
processor reset signal, the writing of data to or from U1301
is inhibited, and a bright digit may be displayed on the
DC 501 0's front panel.
When the positive edge is detected on pin 1 of U1301,
the internal mask interrupt flag will be set and the micro-
.
processor will load its internal program counter from the
reset vector address listed in Table 3-2. This is the start
location for program control.
lnterrupt Vector
(m)
lntegrated circuit U1410 has two internal registers for
interrupt control, an interrupt enable register and interrupt
flag register. Corresponding bits in these registers are logi-
cally ANDed to set an interrupt request pending flag. When
U1410 detects the pending flag bit, it asserts pin 4 as a low
output, generating an interrupt request to the micro-
processor.
When a low level is set on pin 4 of U1410, the micro-
processor completes the current instruction before recog-
nizing the interrupt request and examining its own interrupt
mask flag bit. If the interrupt mask flag bit is not set, the
microprocessor starts an interrupt routine. The contents of
its program counter and status register are temporarily
stored in RAM, the interrupt mask flag bit will be set to
prevent further interrupts, and the program counter will then
be loaded with the high and low bytes of the interrupt vector
address listed in Table 3-2. This is the start location for the
interrupt routine for U1410.
Table 3-2
DC 501 0 INTERRUPT VECTORS
Vector ~ d d r e s s ' Type of Interrupt
$FFFE
-
$FFFF
Interrupt Request (U1410)
'
Dollar sign ($) indicates that address code is in hexidecimal
notation.
There are three possible reasons why U1410 sets an in-
terrupt pending flag, two external events and one internal
event. The two external events are: a negative edge detect-
ed on pin 36 (CH B SLOW) or a negative edge detected on
pin 37 (Display lnterrupt Clock); the one internal event oc-
curs when the 16-bit counter inside U1410 overflows.
Address Decoding
The microprocessor addresses Ul610, Ul410, and
U1313 when communicating with the instrument functions. --.
Table 3-3 lists the hexadecimal address ranges for these
devices.
REV OCT 1981