Tektronix DC 5010 Anleitung Seite 254

Theory of Operation-DC S O
1
0
Logic gate U1313B, along with address bit A15, is used
to enable or disable the proper memory space during the
communication process. When pin 5 of U1313B and pin 6 of
U 131 1 are low (A1 5
=
O), the microprocessor is using the
low memory space on the Digital board to communicate
with the instrument's internal functions. When A15 is high
(=I), the upper memory space on the GPlB board is used
to communicate with other instruments on the IEEE 488
Digital Interface. Logic IC U1311 operates as a three-line to
four-line decoder to select the proper memory spaces that
have starting addresses of C000, D000, E000, and F O O O
(see Table 3-5). The memory devices associated with these
addresses are indicated as such on Diagram 12. The inter-
rupt vector addresses for U1301 are FFFA through FFFF.
The GPlB controller, IC U1101, performs the interface
functions between the microprocessor and other devices on
the bus. Due to its internal architecture, it relieves the micro-
processor from the task of maintaining the protocol as de-
fined in the IEEE 488-1978 standard. The handshake pro-
cess is handled automatically within U1101.
The GPlB output lines, pins 22 through 29 and 31
through 38 on U1101, are connected to the IEEE 488 bus
via tranceivers U1001 and U1002. The direction of data flow
is controlled by the talk enable (TE, pin 21) and CONTROL-
LER (pin 30) outputs generated on U1101. Since the
IEEE 488 controller function is not implemented in the
DC 5010, pin 30 is always false (high). The TE line will be
high for talk, low for listen. The TE and CONTROLLER out-
puts are routed within U1001 and U1002 so that the internal
buffers for particular lines are controlled as required. Tran-
sistor Q1101 operates as an output buffer for the TE signal.
Pins 9 and 10 on P I 001 are not connected to the IEEE 488
Digital Interface; they are reserved for future use.
Communication between the microprocessor and U1101
is carried out with thirteen internal, memory-mapped regis-
ters in U1101. Fourteen internal registers are available, but
one register (parallel poll) is not used. A microprocessor
read operation passes control data back to U1301, while
the write operation passes status information or measure-
ment data to the IEEE 488 bus.
The three least significant address bits (AO, A1
,
A2) con-
nected to pins 6, 7, and 8 of U1101 determine the particular
register selected. The high order address bits (A15, A14,
A13, A1 2) are decoded by U1311, U1312C, U1313A, and
the system clock to cause pin 3 of U1101 to go low for a
read or write operation on an internal register. Reading and
writing to the same location will not access the same regis-
ter within U1101, since they are "read only" or "write only"
registers. When reading a register internal to U1101, the
microprocessor sets pins 4 and 5 high; when writing to a
register, pins
4
and 5 are set low.
Each device
on
the IEEE
488
interface is given a five-bit
address (A1-A5) enabling it to be addressed as a talker or
, -
listener. The DC 5010 address and end-of-message termi-
nator (TC) is set on S1210 (located on the digital board,
Diagram 9) before power-up. The switch, S1210, located on
the GPlB board (Diagram 12) is not used in the DC 501 0.
For more details, refer to the GPlB board (Diagram 12) and
to the GPlB switch discussion in the Maintenance section.
As part of the system initialization procedure, the
microprocessor enables U1310, reads the address that was
set, and stores it in an internal register of U1101. When
U1101 detects the DC 501 0 talk or listen address on the
interfa.;e, it responds by entering the required addressed
state and generating an interrupt signal (IRQ, pin 9) to the
microprocessor. Interrupts to the microprocessor from
U1101 are generated by the following.
A data byte has been received (byte input).
U1101 is ready to accept the next (or first) data byte
for output.
EOI has occurred with ATN
=
0.
Interface Clear (IFC) has been received.
A remote/local state change has occurred.
A Group Execute Trigger command (GET) has been
received.
An Unidentified Universal command has occurred.
An Unidentified Addressed command has occurred.
Device Clear Active State (DCAS) has occurred.
A Serial Poll Active State (SPAS) has occurred with
data bit 7 set in the serial poll register.
NOTE
For more complete and specific details concerning the
internal registers and architecture for U 1 101, refer to
the manufacturer's literature for the 9914 micro-
processor.
Table 3-5
DC 501 0 MEMORY ADDRESS RANGES
'
Dollar sign ($) means that address code is in hexadecimal
notation.
Hexadecimal
Address Range'
$COO0
-
$COFF
$DO00
-
$DO08
$E000
-
$EFFF
$FOOO
-
$FFFF
REV JUL 1983
Comments
U1210 (256 X 8 RAM)
U l 101 (GPIB IC)
U1102 (4K X 8 ROM)
U1201 (4K X 8 ROM)