Tektronix DC 5010 Anleitung Seite 248

Theory of Operation-DC
501 0
modulated by the noise signal generated by
U1410.
For the
other remaining functions, transistor Q1300 is turned off,
U1410 is disabled, and U1400 operates only as a buffer
stage.
The 1 MHz squarewave signal from U1400 (pin 7) is ap-
plied to pin 1, U1021 with the negative edge (falling edge)
used as a reference edge for the Phase Locked Loop (PLL)
U1021. This IC compares the signals negative edge (pin 1)
with the positive edge (pin 3) and produces an output pro-
portional to the phase difference between these two input
signals. The output at pins 5 and 10 (U1021) is then filtered
by a low pass filter with its bandpass providing the proper
phase noise bandwidth for time interval measurements. This
filter, U1030A with associated components, is amplified and
inverted by operational amplifier U1030B. The amplifier out-
put is a dc level proportional to the phase difference be-
tween the 1 MHz reference and the output of the PLL
multiplier. The dc level voltage is coupled to a Colpitts oscil-
lator circuit, Q1130 and associated components, and is in-
ductor-tuned by the varactor diode, CR1130, and series
capacitor C1032. The PLL adjusts the varactor diode volt-
age, which adjusts the oscillator frequency producing a pre-
cise 320 MHz output signal. The oscillator output is ac
coupled to U1022A and a threshold reference voltage is
generated by sensing the complementary outputs of
U1022C through resistors R1021 and R1036. The voltage,
at the junction of these two resistors, establishes this
threshold reference at pin 3 of U1022A. The oscillator out-
put rate on pin 3, produces a 320 MHz reference sinewave
from pin 8. This sinewave is the clock that is counted for the
different measurement modes of the counter. The 320 MHz
signal is applied to pin 1 of U1022B (a setlreset latch that
resets itself at 320 MHz, and buffers and provides proper
ECL drive). This signal is then divided down to 160 MHz at
pin 12, Q1022B. Another divide-by-two (-2) IC, U1022C,
results in an 80 MHz output. This output is ac coupled to
U1020, pin 7 and divided-by-eighty, (+80) producing the
1 MHz signal at pin 2. Any error in output at pin 2 of U1020
is sensed by U1021. This sensed voltage, applied to varac-
tor diode CR1130, adjusts the Colpitts oscillator producing
the precise 1 MHz signal at pin 3 of U1021.
D/A9s, 50
Q
PROTECT, ND ARMING
DIAGRAM
$
The isolation resistors for the 50 Q Protect A (B) sense
lines were discussed earlier (Diagram 1). The sense lines are
routed from the Analog board to the Auxiliary board via
jacks J1510 and J1520.
The 50 Q Protect circuit is composed of a quad compara-
tor (U1111) with associated components. Two of these
comparators are arranged as "window" comparators (Chan-
nel A and B), that receive the protect sense levels from the
Channel A or B inputs. These voltage sense levels normally
operate within a
+2
V window. If the sense levels go out-
side this window (high or low), the comparator output
-
-
changes states (to a low state) and issues a 50
Q
A (B)
PROTECT signal to the microprocessor. The microproc-
essor recognizes this protect line and automatically changes
the input relays from the 50 Q TERM to the 1 MQ TERM.
Trigger levels (CH A LEVEL and CH B LEVEL) are estab-
lished, using a 10-bit D/A converter, U1210 and U1310
(Channel A and B). The data (SERIAL DATA lines) are re-
ceived from the microprocessor through serial-to-parallel
converters U1010 and U1020 (Channel A and B
-
see Dia-
gram 7). These parallel output lines (Diagram 6) form the
digital word that is applied to the D/A converter. The digital
word corresponds to a unique current that is sinked at pin 3
of the D/A converters (U1210, Channel A; U1310, Channel
B). This current, appearing at pin 2 of the operational ampli-
fier circuits, U1200A (Channel A) and U1200B (Channel B),
is converted to a voltage. This voltage can be offset by po-
tentiometer R1205, (R1207, Channel B) and the voltage
range adjusted by potentiometer R1204 (R1206, Channel
B). The output of U1200A (U1200B) at pin 1 is the trigger
voltage that is routed to the amplifier circuitry on the Analog
board (see Diagram 1).
The arming circuit input load (Diagram 6) is 1 standard
TTL load. The input is positive overvoltage protected by di-
ode CR1510 (reverse biases upon receiving an excessive
,-
positive overvoltage). Diode CR1511 is the negative over-
voltage protection component (clamps the output to a diode
below ground) and is current limited by resistor R1500.
Transistors Q1510 and Q1511 form a Schmitt trigger
providing noise immunity to the arming inputs (ARM In and
EXT ARM IN). The
ARM
output signal is routed to the digital
circuitry (Diagram 3).
RELAY DRIVE-DIAGRAM
@
The serial-to-parallel converters, U1010 (Channel A) and
U1020 (Channel B), are used to change the serial data from
the microprocessor to the parallel daa. This data will select
the particular relay to be activiated. The converter output
data are applied to U1110 (U1020, Channel B) that consists
of seven Darlington NPN transistors (shown as inverters).
These devices are used as current sinks to drive the relay
coils. With one end of the selected relay coil brought low via
one of the inverters (U111 O), a voltage pulse is applied to
the opposite coil end. This voltage pulse is generated by the
microprocessor (see Diagram 9) and then amplified and reg-
ulated by the pulse amplifier circuit consisting of transistors
Q1031, Q1030, (21032 and associated circuitry (Diagram 7).
The pulse is approximately 8 V in amplitude with a 25 ms
- .
width; therefore, when a relay coil is energized, the inverter
output is brought low and the microprocessor pulses the
REV JUL
1983