Tektronix DC 5010 Anleitung Seite 253

Theory of Operation-DC 50 10
Each digit and annunciator in the display, each push-
button LED, and each control or pushbutton is assigned a
time slot period approximately equal to the period between
successive interrupts. The time slots are generated by
U1121, a decade counter with 10 decode decimal outputs.
The counter provides time slot decoding for scanning the
front panel controls and multiplexing the seven-segment
LEDs and LED annunciators located on Diagrams 10 and
11. The logic high outputs of U1121 are buffered by nine
Darlington amplifiers (Q1121, Q1122, etc.)
Each interrupt signal causes the microprocessor to clock
U1121 with a negative pulse of approximately 500 ns on pin
14, advancing the count to the next time slot. Immediately
after clocking U1121, the microprocessor updates the digit
associated with that time slot by sending data to U1112 and
U1111, which contain six D-type flipflops each. Data are
latched in U1112 and U1111 when pin 9 goes low and trans-
fers to the outputs on the positive edge of the CLOCK
signal.The BCD output of U1112 is then decoded to seven-
segment information by U1101. Data latches into U1111
and are inverted and buffered by U1110 to drive the decimal
point (DP), the pushbuttons, and annunciator LEDs. The
display drive power supply filter is a pi-network consisting of
C1022, L1020, C1020, and C1021 (Diagram 8). This filter
circuit prevents display noise pulses from disturbing the
sensitive instrument circuits.
After updating the display and checking the front panel
status, the microprocessor returns to the routine of re-
setting the input circuits (if necessary), monitoring the mea-
surement cycle, or collecting the data for the selected
function. This continues until the next front panel interrupt
signal occurs, when it again clocks U1121 for the next time
slot and repeats the procedure.
DISPLAY-DIAGRAM
@
The nine digits in the display are seven-segment, com-
mon anode LEDs; DS1001 is the Most Significant Digit
(MSD) and DS1301 is the Least Significant Digit (LSD). The
time slot lines (previously discussed) are generated by a
nine-state decade counter, U1121 (diagram 10). The micro-
processor sends all 1's (Dl -D4) for the seven-segment infor-
mation when leading zero suppression is indicated. All 1's
are decoded by U1101 (Diagram 9) as a blank.
To illuminate the proper LED or indicator in the display,
the microprocessor sets pins 9, 25, 30, 33, and 36 of PI001
low only during the time slot that corresponds to the dis-
played units of measurement or indicator.
The pushbutton switches are common to one of the four
sense lines (MISC, FUNCTION, RELAYS, and MORE). The
microprocessor senses the switch closure during an active
time slot (logic high) by addressing U1310 (tri-state buffer).
The illumination interval of the GATE light (DS1034) dur-
ing time slot six, is only approximately equal to the actual
measurement gate interval. The GATE light is turned on and
then off only to tell the operator that the counter has been
triggered and that the microprocessor has completed the
functional measurement for the selected number of aver-
ages. The gate light is not directly connected to the actual
hardware gate.
GPIB-DIAGRAM
@
The GPlB circuit board (A14 assembly), with micro-
processor U1301, controls the operating system for the
instrument.
Two ROMs (U1102, U1201), one RAM (U121.0), and a
9914 GPlB controller IC (U1101) are used to communicate
with the IEEE 488 Digital Interface.
The microprocessor recognizes, accepts, and decodes
commands (keypushes and control settings) from the front
panel logic circuits on Diagram 10 and sets the operating
parameters in response to these commands.
The microprocessor is an 8-bit parallel processor with an
8-bit data bus (DO-D7, pins 26 through 33), and a 16-bit
address bus, AO-A15 (pins 9 through 20 and pins 22
through 25). The data bus is bidirectional; the address bus
is not. The address bus is used by the microprocessor to
address the other internal functions of the instrument. The
16 address lines provide up to 76,000 discrete addresses,
commonly referred to as 64 kilobytes of memory. Basically,
any device addressed by the microprocessor is considered
to be a memory device.
System Clock. The microprocessor contains a single
phase internal clock generator (U1301, pins 37 and 39)
whose 1 ps period (approximately is controlled by inverter
U1312D and the rc feedback network consisting of R1301
and C1302. An instruction cycle consisting of two to twelve
machine cycles is required to fetch and execute the instruc-
tion words or data from memory. A machine cycle is defined
as the interval between two successive negative-going tran-
sitions of the system clock. The number of machine cycles
required depends on the instruction and addressing modes
used for the microprocessor.
NOTE
Due to the complexity of the internal operation of the
internal operation of a microprocessor, a detailed de-
scription of U 1301 will not be attempted in this man-
ual. If more detailed information is needed, refer to the
manufacturer's data sheet.
REV OCT 1981