Tektronix DC 5010 Anleitung Seite 246

Theory of Operation-DC 501 0
gates function exactly as they did in
WIDTH A
(and de-
scribed for TlME A
+
B). With U1001 C enabled on pin 18,
the Channel A pulse widths are counted in the Channel A
accumulator while the Channel B events are counted in the
Channel B accumulator. In EVENTS B DUR A the instru-
ment is counting Channel B events only during Channel A
pulse widths and averaging by the selected number of
Channel A events.
When the selected or auto averages condition has been
satisfied, the microprocessor sends the gate signal on pin
15 of U1000C high. The next Channel A trailing edge dis-
ables U1000B (pin 2 high) and the succeeding Channel B
edge sets a low on pin 12 of U1000B. This completes the
measurement cycle.
TlME MANUAL and TOTALize A
For the TlME MAN and TOTAL A functions, the micro-
processor asserts the gate signal on pin 15 of U100C after
the MEASUREMENT STARTISTOP pushbutton on the
front panel is pressed to start the measurement. The gate is
unasserted (set high) when the pushbutton is pressed to
stop the measurement.
For the TlME MAN function, (21114, Q1100, and
U111OC are enabled. Immediately after asserting the gate
signal, the microprocessor momentarily changes the Chan-
nel A triggering slope from its current setting to the opposite
setting and then back again. This change provides an artifi-
cial Channel A signal that enables U1000C and allows the
320 MHz clock signal count to be accumulated in the Chan-
nel B accumulator. The accumulation continues until the
measurement is stopped, at which time the microprocesor
unasserts the gate signal and provides another trigger slope
change to disable U1000C. This stops the accumulation of
time base clock count. Throughout the measurement, the B
Channel is continually red and then directly displayed with
the proper annunciator illuminated.
While taking this reading, the display will occasionally
flicker during the measurement. This is not the result of mis-
counting by the Channel A or Channel B accumulators; the
correct count will be displayed when the measurement is
finished.
For the TOTAL A function, (21114, Q1100, and Q1112
are enabled. When the gate signal is asserted, Channel A
events are counted (totalized) in the Channel A accumulator
until the measurement is stopped. In this case, the micro-
processor does not read the Channel B accumulator; only
the Channel A accumulator counts are displayed. Display
scaling is accomplished by the microprocessor using the
AVGS setting to select the desired scaling factor (power-of-
ten). This scaling is independent of the actual counting pro-
cess and can be changed during or after a measurement
without affecting the count. Thus, the full 13 digits of the
-
internal count chain can be examined by changing the
AVGS exponent. Time, frequency units, and decimal point
are not displayed for this function.
PROBE COMP and TEST
For the PROBE COMP function, the operator applies
probe compensating signals to either Channel A or Channel
B. For either of these modes, the counter is set up (internal-
ly) in RATIO B/A mode. This allows the Channel A or Chan-
nel B signals to pass straight through to the accumulators.
For the TEST function, the microprocessor generates ar-
tificial signals by programming the digital-to-analog convert-
ers (Diagram 6) through their full range. The outputs of the
digital-to-analog converters are applied as trigger level
changes to the differential amplifier circuits in the Channel A
and Channel B Amplifiers (Diagram 2) and end up as counts
in the two count chains. If an illegally large signal is present
on an input (a signal beyond the range of the digital-to-ana-
log converters), this process does not produce counts, and
the TEST may fail. When a failure is indicated, all inputs
should be disconnected and the TEST rerun.
A complete description of the self test function is in the
Maintenance section. Front panel procedures for the
--
PROBE COMP function are found in the Operating
Instructions.
CHANNEL A AND
The Channel A and Channel B accumulators are two
nearly symmetrical binary ripple counters, each having the
capabilities for its contents being "read" serially by the
microprocessor. Each accumulator begins with high speed
ECL. Then, as the maximum toggle rates decrease, goes to
medium speed ECL, then to LS TTL, and eventually CMOS.
Wherever possible, a counter IC of a given family is shared:
one half is used by Channel A and one half by Channel B.
The Channel A accumulator begins on the Analog board
(A1 2) with signals clocking U1 OOOA, pin 5 (see Diagram 3).
The Channel B accumulator signal clocks UlOllC, pin 1.
The first two binary stages for each accumulator are ECL
100k and consist of U1000A and U l 01 1 A (Channel A) and
U1011 C and U1011 B (Channel B).
The counts (CH A FAST and CH B FAST) are routed
from the Analog board to the Digital board (A16) through
--
coaxial cables (W520 and W530). The next two binary
stages for each count chair) are ECL 10k and use IC's
REV OCT 1981