Tektronix DC 5010 Anleitung Seite 22

Characteristics
Arming lnput
Required Signal lnput
Pulse Response
Shaped Output
External Clock lnput
10 MHz Clock Output
Table 1-1 (cont)
Performance Requirements
low ~ 0 . 4 volts
high a2.4 volts (TTL)
Pulse width a 1 00 ns
a 5 0 0 mV rms into 1 kQ (ac coupled)
1, 5, or 10 MHz
low ~ 0 . 4 V
high 32.4 V (TTL)
(pins 15B and 15A (gnd))
Phase Modulated Clock
(time interval functions)
STANDARD INTERNAL TlME BASE
Frequency at calibration
Error Terms
Temperature Stability
(0°C to +50°C)
Aging
Adjustment Resolution
Frequency at calibration
Error terms:
Temperature Stability
(0°C to +50°C)
Warm-up Time
Supplemental Information
Maximum voltage Vpk <10 volts.
a 1 0 0 mV typically to :350 MHz
into 50 Q load. Delay from
front-panel input to shisped output.
CH A 7.2 nsec typicalky
CH B 7.0 nsec typicallly
CH B commoned from CH A
7.6 nsec typically.
Drives 1 TTL load.
a 3 ns p-p jitter induced
onto 1 MHz reference. (Test
point on rear of Auxi1ia.r~
board.)
10 MHz
OPTIONAL INTERNAL TlME BASE
10 MHz +2
x
+
2
x
1 after warmup
Within
+
2
x
1
of final
frequency in less than 10 minutes
when cold started at 25°C ambient.
With proportional oven
R;EV OCT 1981