Tektronix DC 5010 Anleitung Seite 244

Theory of Operation-DC 501 0
MAIN GATING-DIAGRAM
@
The microprocessor controls the measurement gate in-
terval through the
GATE
signal going to pin 4 of U111 OB.
The IC's U1000C and U1000B operate as synchronizers to
ensure that the accumulator gates, U1001 C and U111OA
open and close at the proper time for the desired measure-
ment. Synchronizing the accumulator gates with the signals
to be counted ensures that the accumulators will contain a
count corresponding only to a whole number of input and
time-base pulses. In the absence of the synchronizers, the
gates would sometimes pass fractional pulses, and the
count chains might not be able to make a reliable count. The
signals to be counted clock the synchronizers at pin 16,
U1000C and pin 1, U1000B.
Before each measurement is initiated by the micro-
processor, U 1 000C and U 1 000B are set by a M R, (Master
Reset) pulse on connector J1010 pin 1. The IC's UlOOlC
and U111 O A are thus disabled by the high level synchronizer
outputs at pins 14 (U1000C) and 1 1 (U1000B) until the mea-
surement begins.
For those modes that use the Channel A Amplifier with
positive slope triggering, negative going edges are generat-
ed on pin 6 of U1001 B. Pin 7 of shift register U1200 is
latched high for all operating modes except the time interval
modes (TIME A+B, WIDTH A, RISEIFALL Time, and
EVENTS B DUR A). With pin 7 of U1200 high, U1210D pin
12 is low, so Q1114 is enabled. The Channel A signal is then
inverted by U1001C and clocks U1000A on pin 5. The
Channel A complement signal appearing on pin 6 of
U1001 B, is inverted by U1001 E and clocks the synchronizer
flip flop U100C pin 16 after passing through U1001 D.
NOTE
Transistors Q1110, Q1114, Q1111, Q1112 and
QlOOO operate as switches to route the Channel A,
Channel B, and 320 MHz time base signals through
the proper logic gates for the selected front panel
function. These transistors are either completely "on"
or completely "off", depending on whether their base
resistors are pulled high or low. Transistor Q 1 100 is
used to disable U 1001A. See Table 3- 1.
FREQ A
and
PERIOD A
If the
GATE
signal from the microprocessor (U1200 pin 4)
and the arming signal
(m)
on J1102-1 are both low, a low
is set on the D input (pin 15) of U1000C after passing
through U111OB. This low is transferred to pin 14 on the
first Channel A edge that clocks U1000C after the measure-
ment gate started. The low on pin 14 enables the second
synchronizer, U1 OOOB, and the Channel A accumulator
gate, U1001 C. With U1001C enabled, the next negative
edge of the Channel A signal is allowed to pass through
-
UlOOlC, gets inverted, and is counted by the first binary
stage of the Channel A accumulator (U1 OOOA, pin 5).
For the FREQ A and PERIOD A functions, pin 14 of shift
register U1200 is latched low. This turns on U111OC and
turns off Q1112, allowing the 320 MHz time base signal to
clock U1000B on pin 1. The first positive time base edge to
clock U1000B after U1000C changed state, sets a low on
pin 11 of UlOOOB, enabling the Channel B accumulator
gate, U111 OA. The next negative edge of the 320 MHz time
base signal then passes through U111OA in its inverted
form and is counted by the first binary stage of the Channel
B accumulator (U1011 C).
Table 3-1
SIGNAL ROUTING SWITCHING LOGIC FOR U1200
(X
=
low, blank
=
high)
PIN NUMBERS
Function
FREQ A
PERIOD A
WIDTH A
TlME MAN
TlME A
+
B
RISEIFALL A
RATIO B/A
TOTALA, A+B, A-B
PROBE COMP
EVENTS B DUR A
After the synchronizers and accumulator gates have
been enabled, all succeeding input pulses are counted by
the Channel A accumulator and all succeeding time base
pulses are counted by the Channel B accumulator.
The counting process continues until the selected num-
ber of averages have been satisfied or the time out period,
while in the auto mode, has been satisfied. At this point, the
gate signal from the microprocessor goes high, setting the D
input (pin 15) of U1000C high. The next positive edge of the
Channel A input signal then clocks U1000C and pin 14 goes
high, disabling U1000B and U1001C. The next 320 MHz
time base edge then clocks U1 0008, disabling U111 O C and
sending END low alerting the microprocessor that the mea-
surement cycle has ended.
When the measurement cycle has ended, the micro-
-
processor reads the total counts in both accumulators. The
Channel A accumulator contains the number of events or
REV JUL 1983