Tektronix DC 5010 Anleitung Seite 245

Theory of Operation-DC 50 10
periods and the Channel B accumulator contains the num-
ber of time base clock pulses counted over the same inter-
val. The microprocessor divides the number of events in the
.
Channel A accumulator by the total time in the Channel B
accumulator to obtain the frequency (FREQ A) or divides the
total time in the Channel B accumulator by the number of
events in the Channel A accumulator to obtain the period, or
time per Channel A event (PERIOD A).
RATIO B/A
The RATIO B/A mode is the same as FREQ A and PERI-
OD A, except that instead of counting 320 MHz time base
pulses, U111 O C is disabled by a high on pin 14 of shift regis-
ter U1200, and Q1112 is enabled by a low from inverter
U1210E. This allows the Channel B signal to clock U1000B.
The counts are accumulated over the time interval deter-
mined by the number of averages selected. The RATIO B/A
result is then calculated by dividing the number of Channel B
events by the number of Channel A events. The AVGS ex-
ponent refers to the count in Channel A.
TlME A
- ,
B
For the TlME A
- +
B function, Q1110 and Q1112 are
disabled; Q1111, Q1114, Q1000, U1001 E, U111 OC, and
U1001 D are enabled. The first Channel A pulse slope that is
selected, is inverted by UlOOlB, inverted again by
U10001 E, and then applied to pin 19 of U1001 D. The syn-
chronizers have been set by the MR, (Master Reset) pulse
and the Channel A pulse clocks on pin 16 of U1000C.
As soon as the gate signal from the microprocessor sets
pin 4 of U111OB low, the next Channel A clock edge to
U1000C transfers the low on pin 15 to pin 14 and sets pin
13 high.The high on pin 13 passes through Q1000, disables
U1001 E, and prevents U1001 D from being clocked by suc-
ceeding Channel A pulses. The Q output of UlOOOC (pin
14), being low, enables U1001A and allows the first suc-
ceeding Channel B pulse edge to clock UlOOOC via
U1001 D, setting pin 14 high and pin 13 low again. Pin 13,
going low with the Channel B edge, also re-enables U1001 E
again for the next Channel A edge to clock U1000C.
During the period of time that pin 14 of U1000C is low,
U1000B is enabled. The 320 MHz time base clock pulses
are synchronized and gated by UIOOOB and U11 IOA, and
then counted by the binary stages in the Channel B accumu-
lator, beginning with U1011 C.
Since Q1114 is disabled, U1001 C is enabled with a low
on pin 17 and also enabled each TlME A
+
B interval ap-
pears as a negative pulse on pin 18. This negative time
interval pulse is converted to a positive time interval pulse
by U1001 C and then counted by the binary stages in Chan-
-
nel A accumulator. Thus, for each TlME A
+
B interval, a
count is accumulated in the Channel A accumulator; and
during each of these intervals, the 320 MHz clock pulses are
accumulated in the Channel B accumulator.
The microprocessor is continually reading the counts (ac-
cumulated time intervals) in the Channel A accumulator.
When it finally reads a count greater than or equal to the
selected number of averages (loN) or when the measure-
ment time in the auto mode ( ~ 0 . 3 seconds) has been satis-
fied, the microprocessor sets the gate signal on pin 4 of
U111 O B to a high level. The next Channel A pulse clocks a
high through U1000C to pin 18 of U1001 C and disables
U1000B. The next 320 MHz clock pulse then toggles
U1 0008, disabling U111 O A and allows the
END
signal line
(J1102-1) to go low. This alerts the microprocessor that the
measurement cycle has been completed. The micro-
processor then makes a final reading of both accumulators,
divides the total time by the number of intervals, and up-
dates the display during the next measurement cycle.
WIDTH A
The WIDTH A function is essentially the same as the
TlME A
+
B except that Q1110 is enabled. This then al-
lows the leading edge of the Channel A pulse width to be
measured, and applied to pin 23 of U1001 E and the training
edge to be applied to pin 2 of UlOOlA, through the 3.5 ns
delay line (DL 500).
The synchronizers (U1000C and U1000B) and the accu-
mulator gates (U1001 C and U111 OA) function exactly like
they did in TlME A
+
B. The pulse widths are regenerated
on pin 14 of U1000C and during each of the negative pulse
intervals, U1000B and U1001C are enabled so that the
320 MHz clock pulses (via Q111 OC) can be counted by the
Channel B accumulator. Also, each regenerated pulse is
passed through U1001 C and counted by the Channel A ac-
cumulator. Again, when the average conditions have been
satisfied, the microprocessor stops the measurement gate,
reads both the accumulators, and divides the total time by
the number of regenerated time intervals to obtain the aver-
age pulse width.
EVENTSBDURA
The EVENTS B DUR A function is the same as WIDTH A
except that instead of counting 320 MHz clock pulses via
U11 IOC, the instrument is counting Channel B events dur-
ing the selected Channel A pulse width via Q1112. To do
this, Q1110, Q1112, and Q1000 are enabled. The leading
and trailing edges of the Channel A pulse are again applied
to pin 23 of U1000E and pin 2 of U1001 A.
The Channel 8 signal passes through Q1112 to clock the
second synchronizer, U1000B. When the gate signal on pin
15 of U1000C goes low, the synchronizers and accumulator
REV JUL 1983