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Verfügbare Sprachen
Verfügbare Sprachen
Test Point
Net Name
TP496
CPU_A4
TP497
CPU_A5
TP498
CPU_A6
TP499
CPU_A7
TP300
CPU_A8
TP301
CPU_A9
TP302
CPU_A10
TP303
CPU_A11
TP304
CPU_A12
TP305
CPU_A13
TP306
CPU_A14
TP307
CPU_A15
TP308
CPU_A16
TP309
CPU_A17
TP310
CPU_A18
TP311
CPU_A19
TP312
CPU_A20
TP313
CPU_A21
TP314
CPU_A22
TP315
CPU_A23
TP350
NCEO_A
TP351
EN1_A
TP352
EN0_A
TP353
VCC3_EN_A
TP354
VCC5_EN_A
TP401
I_FLAG_A
TP365
INIT_DONE_A
TP364
RDNBSY_A
TP372
CLKUSR_A
TP355
CONF_DONE_C1
TP456
RESET_A
TP457
A4_A
TP373
A2_A
TP374
A_PLL_2
TP458
DATA_CI
TP375
DEV_CLRN_A
TP459
/CS_1EEE1394
TP460
/CS_CI_B
TP376
CD7
TP493
CD6
TP492
CD5
TP491
CD4
TP479
CD3
TP478
CD2
TP477
CD1
TP476
CD0
Sheet 5
Video/Audio Output
TP504
SCRESET/RTC
TP515
TTXREQ
TP514
TTXDATA
TP516
RSET
TP500
/VSYNC_AV
TP502
ALSB
2
TP513
I
C_ADDRESS
TP503
/PALENC_AV_RESET
TP512
COMP
TP528
VREF
TP544
SCL
TP548
SDA
TP506
R/C
TP507
G/Y
TP508
B/CVBS
Function
Main CPU address bit 4
Main CPU address bit 5
Main CPU address bit 6
Main CPU address bit 7
Main CPU address bit 8
Main CPU address bit 9
Main CPU address bit 10
Main CPU address bit 11
Main CPU address bit 12
Main CPU address bit 13
Main CPU address bit 14
Main CPU address bit 15
Main CPU address bit 16
Main CPU address bit 17
Main CPU address bit 18
Main CPU address bit 19
Main CPU address bit 20
Main CPU address bit 21
Main CPU address bit 22
Main CPU address bit 23
CI 1 Configuration complete enable
CI 1 VPP enable 1
CI 1 VPP enable 0
CI 1 VCC 3V3 enable
CI 1 VCC 5V enable
CI 1 Error indication IC401
CI 1 Initialisation complete
CI 1 configuration ready line
CI 1 optional initialisation clock
CI Configuration ready/complete
CI 1 Reset module CPU
CI 1 Address Bus Bit 4
CI 1 Address Bus Bit 2
Audio PLL select 2
CI Configuration data
CI 1 enable register clear
Chip select IEEE1394 LLC
Chip select CI 2
Transport stream data FE to CI 1 bit 7
Transport stream data FE to CI 1 bit 6
Transport stream data FE to CI 1 bit 5
Transport stream data FE to CI 1 bit 4
Transport stream data FE to CI 1 bit 3
Transport stream data FE to CI 1 bit 2
Transport stream data FE to CI 1 bit 1
Transport stream data FE to CI 1 bit 0
Sub carrier reset/real time control mode
Teletext data request signal
Teletext data input
Setting for full scale amplitude of video signals
Field/V synch
TTL address input
2
I
C_ADDRESS
/PALENC_AV_RESET
PAL encoder comparater input
PAL encoder reference voltage
2
I
C clock
2
I
C data
Red/chroma output from pal encoder
Green/Luma output from pal encoder
Blue/CVBS output from pal encoder
56
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