Hitachi CL32W30TAN Wartungshandbuch Seite 45

MAIN SYSTEM CLOCK AND PLL
The 27MHz from the clock buffer is frequency/phase locked to the incoming datastream using a PLL (IC206, RR225, R223, R222,
R219, C210, C212, C208, C209, C211). The local supply is decoupled through L200, C242, and R219 is used to isolate the local
ground section.
The CPU uses a 54MHz clock internally, this is generated on-board using an internal 'x2' PLL loop. The 54MHz is available for test
purposes at pin 20 / TP218, through R209.
TRANSPORT STREAM DEMULTIPLEXING (L64108)
The functionality of this section covers:
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Parsing the SI data from the transport stream
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Extracting the transport stream packets for the video and audio service
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Buffering the video and audio data onto the AV chip
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Extracting the data packets associated with the graphical objects and images which are to be displayed, or acted on.
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Separation of individual PES streams
This section of the IC contains the functional circuit blocks to carry out the transport stream processing to extract the necessary
information from the SI packets of the transport stream to allow the service to be directly decoded.
It involves parsing the MPEG SI tables which carry all the data about the origin, content, timing and format of the services in the
transport stream. Most of this work is done in hardware under the control of the CPU software tasks.
CPU / Demux Architecture
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