Herunterladen Inhalt Inhalt Diese Seite drucken

Hitachi CL32W30TAN Wartungshandbuch Seite 44

Inhaltsverzeichnis

Werbung

Verfügbare Sprachen

Verfügbare Sprachen

Chip select
Usage
Internal registers
Internal I/O
CS0
Flash bank 1 (2MB) or Boot ROM
CS1
Flash bank 0 (2MB)
CS2
Common Interface A (2MB)
CS miss
Not allocated (4MB)
Peripherals (2MB)
This area is mapped
as shown in the
table on the right
Primary DRAM (2MB)
Address (hex)
100.0000
F0.0000
E0.0000
C0.0000
A0.0000
80.0000
40.0000
Peripheral 2MB address space mapping
Chip
Select
CS miss
CS3
CS miss
20.0000
00.0000
43
Usage
(IEEE1394)
(External DRAM controller)
AV chip decoder
Not Allocated
Common Interface B
Address (Hex)
40.0000
23.0000
22.0000
20.2000
20, 0000

Werbung

Inhaltsverzeichnis
loading

Inhaltsverzeichnis