Hitachi CL32W30TAN Wartungshandbuch Seite 52

Test Point Net Name
TP154 AV_A8
TP155 AV_A7
TP156 AV_A6
TP157 AV_A5
TP158 AV_A4
TP159 AV_A3
TP160 AV_A2
TP161 AV_A1
TP162 AV_A0
TP163 AV_A10
TP164 AV_A11
TP165 /BCS1
TP166 /BCS0
TP167 /BRAS
TP168 /BCAS
TP169 /BWE
TP170 DQM
TP171 LP2
TP174 PLLVDD
TP172 PLLVSS
TP178 LP2 (via resistor)
TP177 GNDD
TP175 CKEA0
TP176 CKEA1
Sheet 2 CPU/Demux
TP1155 5V M-PEG
TP1040 5V_OSC
TP257 MCLK_SDC
TP243 27MHzCLK
TP1034 27MHz OSC2
TP1032 27MHz OSC1
TP256 27MHzOUT
TP254 CLK_27_OSCOUT
TP997 CLK_27_0
TP229 CLK_27_1
TP998 CLK_27_2
TP999 CLK_27_3
TP263 CLK_27_4
TP262 CLK_27_5
TP226 CLK_27_6
TP225 CLK_27_7
TP224 CLK_27_8
TP223 CLK_27_9
TP1067 PDATA_DIR
TP218 MCLK_54
TP1061 MCLK_54_CPU
TP1137 TCK_CPU
TP1141 TCK_CPU
TP264 TDI_CI_DRAMC_LLC
TP265 TMS_CI_DRAMC_LLC
TP266 TDO_CI_DRAMC_LLC
TP267 TCK_CI_DRAMC_LLC
TP268 TRST_LLC
TP215 TDI_CPU
TP214 TDO_CPU
TP213 TMS_CPU
TP212 TCK_CPU
TP211 TRST_CPU
TP234 MPEG_TO_USER_IPL_B
TP235 USER_TO_MPEG_IPL
TP220 18M_CLOCK_RESET
TP201 /CI_RESET
Function
SDRAM address 8
SDRAM address 7
SDARM address 6
SDRAM address 5
SDARM address 4
SDRAM address 3
SDRAM address 2
SDRAM address 1
SDRAM address 0
SDRAM address 10
SDRAM address 11
SDRAM 1 chip select
SDRAM 0 chip select
RAS SDRAM control
CAS SDRAM control
SDRAM write enable
SDRAM data control mask
PLL control
81MHz phase lock loop local supply
81MHz PLL local ground
PLL control
Digital ground
Clock enable, SDRAM 0
Clock enable, SDRAM 1
5V MPEG supply voltage
5Vsupply voltage to 27MHz oscillator voltage
27MHz oscillator feedback
27MHz clock
27MHz oscillator crystal
27MHz oscillator crystal
27MHz oscillator output collector
Biased 27MHz oscillator clock output to buffer IC
27MHz oscillator clock output 0
27MHz oscillator clock output 1
27MHz oscillator clock output 2
27MHz oscillator clock output 3
27MHz oscillator clock output 4
27MHz oscillator clock output 5
27MHz oscillator clock output 6
27MHz oscillator clock output 7
27MHz oscillator clock output 8
27MHz oscillator clock output to CPU PLL
Control for parallel data bus
54MHz clock output after resistor
54MHz clock output direct on IC
JTAG clock to CPU
JTAG clock to CPU
JTAG data input to DRAM
JTAG Test mode set for DRAM controller/IEEE 1394 LLC chip
JTAG data output
JTAG clock input
JTAG reset input
JTAG data input to CPU
JTAG data output to CPU
JTAG Test mode set for CPU
JTAG clock to CPU
JTAG reset to CPU
MPEG to user interprocessor link data
User to MPEG interprocessor link data
18MHz clock reset
/CI_RESET
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