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The control lines are generated on port pins of the Common Interface A chip, with the values being set in one of the command
registers of that device (see section on Common Interface later).
Assuming the input reference frequency is 27MHz, the control protocol for these lines is as in the table following:
Control inputs
FS2
FS1
FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Also see the diagram in the 'AV decoder' section later.
COMMON INTERFACE (CI) CIRCUITRY
The MPEG board has the provision for two common interface sockets CI A (IC400) and CI B (IC402). The implementation of the
Common Interface is undertaken by two Altera FPGA devices, one for each CI port.
UART clock output
(MHz)
Tristate
1.8620
1.8620
1.8620
1.8620
1.8620
1.8620
Low
Overall block Diagram of Common Interface Architecture
Audio PLL clock output
(MHz)
Tristate
256 x 16.0kHz
256 x 22.05Hz
256 x 24.00kHz
256 x 32.00kHz
256 x 44.10kHz
256 x 48.00kHz
Low
38
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