Hitachi CL32W30TAN Wartungshandbuch Seite 56

Test Point Net Name
TP399 D5_B
TP402 MDO3_B
TP461 /CI_RESET_B
TP462 /CONFIG_CI
TP464 VCC5_EN_B
TP465 VCC3_EN_B
TP467 EN1_B
TP400 1_FLAG_B
TP468 INIT_DONE_B
TP367 RDNBSY_B
TP366 CLKUSR_B
TP469 NCS_B
TP470 CS_B
TP471 NWS_B
TP472 NRS_B
TP473 DEV_OE_B
TP474 DCLK_CI
TP475 DEV_CLRN_B
TP377 BCLKOUT
TP379 DVALIDOUT
TP378 FSTARTOUT/NOT_EPROM
TP403 TS_A_B_0
TP404 TS_A_B_1
TP405 TS_A_B_2
TP406 TS_A_B_3
TP407 TS_A_B_4
TP408 TS_A_B_5
TP409 TS_A_B_6
TP410 TS_A_B_7
TP411 TS_A_B_MCLK
TP422 TS_A_B_MVAL
TP423 TS_A_B_MSTRT
TP480 TS2_IN_MSTRT
TP481 TS2_IN_MVAL
TP482 TS2_IN_MCLK
TP483 TS2_IN_7
TP484 TS2_IN_6
TP485 TS2_IN_5
TP486 TS2_IN_4
TP487 TS2_IN_3
TP488 TS2_IN_2
TP489 TS2_IN_1
TP490 TS2_IN_0
TP412 CPU_D0
TP413 CPU_D1
TP414 CPU_D2
TP415 CPU_D3
TP416 CPU_D4
TP417 CPU_D5
TP418 CPU_D6
TP419 CPU_D7
TP420 CPU_D8
TP421 CPU_D9
TP449 CPU_D10
TP450 CPU_D11
TP451 CPU_D12
TP452 CPU_D13
TP453 CPU_D14
TP454 CPU_D15
TP455 CPU_A0
TP463 CPU_A1
TP494 CPU_A2
TP495 CPU_A3
Function
CI 2 Data Bus Bit 5
CI 2 transport stream data out Bit 3
CI 2 Interface chip reset
CI Configuration control input
CI 2 Enable VCC to 5V
CI 2 Enable VCC to 3V3
CI 2 VPP enable 1
CI 2 Error indication IC403
CI initialisation complete
CI 2 configuration ready line
CI 2 optional initialisation clock
CI 2 chip select active low
CI 2 chip select active high
CI 2 write strobe
CI 2 read strobe
CI 2 enable O/Ps to tristate
CI configuration data clock
CI 2 enable register clear
Transport stream packet clock from FE to CI 1
Transport stream packet valid from FE to CI 1
Transport stream packet start from FE to CI 1
Transport stream data CI 1 to CI 2 bit 0
Transport stream data CI 1 to CI 2 bit 1
Transport stream data CI 1 to CI 2 bit 2
Transport stream data CI 1 to CI 2 bit 3
Transport stream data CI 1 to CI 2 bit 4
Transport stream data CI 1 to CI 2 bit 5
Transport stream data CI 1 to CI 2 bit 6
Transport stream data CI 1 to CI 2 bit 7
Transport stream packet clock CI 1 to CI 2
Transport stream packet valid CI 1 to CI 2
Transport stream packet start CI 1 to CI 2
Transport stream packet start IEEE1394 to CI 1
Transport stream packet valid IEEE1394 to CI 1
Transport stream packet clock IEEE1394 to CI 1
Transport stream data IEEE1394 to CI 1 bit 7
Transport stream data IEEE1394 to CI 1 bit 6
Transport stream data IEEE1394 to CI 1 bit 5
Transport stream data IEEE1394 to CI 1 bit 4
Transport stream data IEEE1394 to CI 1 bit 3
Transport stream data IEEE1394 to CI 1 bit 2
Transport stream data IEEE1394 to CI 1 bit 1
Transport stream data IEEE1394 to CI 1 bit 0
Main CPU data bus bit 0
Main CPU data bus bit 1
Main CPU data bus bit 2
Main CPU data bus bit 3
Main CPU data bus bit 4
Main CPU data bus bit 5
Main CPU data bus bit 6
Main CPU data bus bit 7
Main CPU data bus bit 8
Main CPU data bus bit 9
Main CPU data bus bit 10
Main CPU data bus bit 11
Main CPU data bus bit 12
Main CPU data bus bit 13
Main CPU data bus bit 14
Main CPU data bus bit 15
Main CPU address bit 0
Main CPU address bit 1
Main CPU address bit 2
Main CPU address bit 3
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