Hitachi CL32W30TAN Wartungshandbuch Seite 40

Common Interface A (CI A) is always fitted, Common Interface B (CI B) is an optional fit. If CI B is not required it can be bypassed
by a network of resistors (R413 - R418, R420, R421, R423 - R425) on the PCB to route the transport stream direct to the demux IC.
Each chip contains the following circuit functions:
•
Interface between the CPU bus and the 'PCMCIA' style interface on the module
•
Transport stream routing control
•
Control of the CI module power switch IC (IC401, IC403)
•
Internal control register stack
In addition the CI A chip includes:
•
Provision for a second transport stream input and routing control
•
Address decoding to provide chip enables for other devices
•
Control of the audio PLL
INITIALISATION
At power up the FPGA (Field Programmable Gate Array) devices need to be configured. A block of code is clocked to the devices
from the CPU using the SC1 port of the CPU (see section later) using handshaking lines and a 'configuration' register to confirm
correct programming of the devices. The code transferred may be the same for PCBs carrying either one or two devices, if the
second FPGA is not fitted the extra code is ignored by the first device.
Although the FPGAs are programmed devices, after they have been programmed they effectively behave as 'hardware' and will be
referred to 'CI controller ICs'.
Internal control register structure
Both these devices are connected to the CPU via a 16 bit data bus and 24 bit address bus along with the associated control and
handshaking lines.
The transport stream is routed through the CI A and CI B chips in a daisy-chain manner and fed to the demux section of the
CPU/demux IC.
The CI controller ICs each have 4 internal registers to allow the state of the CI to be read/set-up by the CPU. These are as follows:
Register R/W
7
Status R 0
Control 0 R/W X
Control 1 R/W X
Configuration R X
6 5 4
0 0 IRQ
R/rout X TsAB
X S/cyc I/O
X X X
Bit
3 2 1
VS2 VS1 CD2
En1 En0 Vcc3
Reg I/face Int
X 1 1
39
0
CD1
Vcc5
Reset
0