Hitachi CL32W30TAN Wartungshandbuch Seite 42

ADDRESS DECODE FOR CI B.
The chip enable for CI B is generated by the address decode in CI A, this enables the CPU to communicate with CI B and perform
similar CA (Conditional Access) related operations as CI A. The connections to the data and address bus are common to both
devices.
The CI A chip also provides the address mapped chip select outputs for the IEEE1394 and external CPU DRAM options which are
not currently supported in the PCB build.
This address mapping is detailed in the memory map in the CPU section (later).
CI MODULE VOLTAGE SELECT.
These output pins control the setting of the required voltages to the Vcc and Vpp lines for the common interface socket. The value
set depends on the 'VS' pins of the module interface and the configuration information of the CI module when inserted, and the
information is reflected in the bits 2 and 3 of the status register. The values used to control the power supply ICs (IC401, IC403) are
stored in bits 0 - 3 of control register 0. IC401 for CI A and IC403 for CI B switch the actual voltage from the 5V and 3V3 supplies.
IC401 and IC403 internally control the over-current and switching timing for these supplies.
FREQUENCY SELECT LINES FOR THE PLL ASSOCIATED WITH REV C 64108
CPU/DEMUX CHIPS.
Three select lines are used from CI A to set the sample frequency of the audio PLL (bits 0 - 2 of the configuration register).
JTAG TEST CAPABILITY
The CI chips have JTAG test capability. They are configured as part of a 'one loop' or 'two loop' test system with other chips on the
PCB, more details are given in the 'JTAG testing' section (section 2.6) later.
MAIN SYSTEM CPU / MPEG DEMULTIPLEXER (IC200 / L64108)
GENERAL
This IC performs four main functions on the system:
•
Main system CPU
•
Locking of the incoming data to the main system clock and generation of internal 54MHz clock by PLL
•
Transport stream demultiplexing and SI decoding
•
Packet decoding and AV data transfer to the AV chip
•
Separation of PES streams to output to the IEEE1394 interface (for possible future use)
CPU FUNCTIONS
See also diagram in demultiplexer section following.
The system CPU operates internally in 32 bit mode at a clock speed of 54MHz, but with a 16 bit external data bus (E-BUS) and
memory space mapped by 24 address lines operating at 27MHz. It's main function is the maintenance of the software program flow
to control all the devices needed for the functionality of the digital receiver. It has internal cache memory to speed up processing,
and uses external EDO DRAM (2MB) for the main processing workspace. Accommodation for up to 4MB of flash memory is
designed in as two 1M x 16 bit chips. The program start is initiated by the main 'power-on-reset'.
In order to carry out this function and make use of the system resources this requires:
•
Communications with other devices
•
Asynchronous serial communications using RS232 protocol – on-board UARTs are used to communicate with the modem
and the external RS232 level converter on the front-end COFDM PCB via PL200, and with the user processor through the
Interprocessor Link (IPL) on PL203. The operation of the IPL is based on a 'message-and-response' protocol with the
master being the user processor under normal circumstances.
•
Programming port for the CI controller ICs (CI A and CI B) – this uses the pins (SC1x) normally allocated to the second
smart card driver IC, with clock, data, acknowledge, enable and status lines.
•
I2C – the CPU has an integrated peripheral to act as master for the I2C bus for all the devices on the digital section, these
are:
•
Video encoder on the MPEG PCB
•
Tuner on the COFDM PCB
•
COFDM IC on the COFDM PCB
•
FEC IC on the COFDM PCB
•
NVM on the COFDM PCB
Pull-up resistors are provided on the front-end PCB on the COFDM IC and the tuner, and on the video encoder IC (R532, R533)
pulling up to 5V.
•
The E-BUS gives an address space of 2
with and control the other devices on the PCB, this bus is used on the MPEG PCB, by:
•
Flash memory – two chip locations are available on the PCB, but at present only a single 1M x 16bit chip is used. These
positions can accommodate 512k x 16 bit or 1M x 16 bit flash chips operating to the AMD protocol and connections.
•
Common Interface (CI) controller ICs – the one or two devices fitted use the E-BUS both as a control and data/control
interface with the CPU
•
The AV (Audio/Video) decoder – the E-BUS is used for passing audio-video samples from the demux to the AV decoder,
and for the necessary control communications.
•
IEEE1394 fast serial interface, IC600, IC601 (not currently supported)
•
External DRAM controller IC700 / IC701 (not currently supported)
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mapped as in the table earlier in this section in 16 bit wide form to communicate
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