Input Processor - Philips Tda 9320 - Hitachi CL32W30TAN Wartungshandbuch

As the diagram shows, A/B are the Odd/Even original 50Hz signal fields which are used to create extra picture information, while
A*/B* are the predicted/manipulated extra picture information, created by the feature box. Fig.1 shows the differences between
100/120Hz interlaced and 50/60Hz progressive scan. The biggest advantage of progressive scan is "non-interlaced" scanning;
keeping the field frequency at 50/60Hz. This means the line construction is double per field, compared with 100/120Hz interlaced. It
will make very fine pitch scan lines and will eliminate line flicker. The advantage of selecting 100Hz operation will be the reduction of
large area flicker and will reduce the line flicker (except for A8 W30 100Hz models).
This unit is powered from +5V and +8V supplies, feeding into pins 21, 22 and 26 of E10 respectively. The three input 50Hz video
signals Y, U, V are sent to this unit at pins 8, 10 and 12 of E11. The Y, U, V video output signals (double frequency video) are taken
from pins 5, 3 and 1 of E11. The horizontal and vertical sync signals are input to this unit as a composite sync signal at 24 of E10,
the double frequency horizontal and vertical sync signals outputs are from pins 30 and 31of E10.

INPUT PROCESSOR - PHILIPS TDA 9320.

The TDA9320 is a multistandard input processor. Features include:
VIDEO OUTPUTS/EXTERNAL INPUTS.
The input processor has provision for three CVBS inputs (1 internal & 2 external) and 2 Y/C inputs. The external CVBS inputs are
used for the Scart sockets. The Y/C inputs are used for S-VHS and a third CVBS input. The circuit can detect whether CVBS or a
Y/C signal is presented to AV3 input. The I.C. has 2 RGB inputs with fast switching. The switching of the various sources is
2
controlled by I C and detection of a Comb filter can be made.
SYNCHRONISATION.
The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are
fed to the slicing stage which is operating at 50% of the amplitude. The sync pulses are fed to the phase detector and to the
coincidence detector. This coincidence detector is used to detect whether the line oscillator is synchronised and can also be used
for transmitter identification. The PLL has a very high statical steepness so that the phase of the picture is independent of the line
frequency.
For the horizontal output pulse, two conditions are possible:
An H pulse which has a phase and width which is identical to the incoming horizontal sync pulse.
A
A clamp pulse CLP which has a phase and width which is identical to the clamp pulse in the sandcastle pulse.
The H /CLP signal is generated by means of an oscillator which is running at a frequency of 440 x F . Its frequency is divided by
A H
440 to lock the first loop to the incoming signal. The free running frequency of the oscillator is determined by a digital control circuit
which is locked to the reference signal of the colour decoder. When the coincidence detector indicates an out of lock situation the
calibration procedure is repeated.
The vertical pulse is obtained via a vertical count down circuit. The countdown circuit has various windows depending on the
incoming signal (50/60Hz).
VISION I.F. AMPLIFIER.
The video signal is demodulated by means of a PLL carrier regenerator. This circuit contains a frequency detector and a phase
detector. During acquisition the frequency detector will tune the VCO to the right frequency. After lock-in, the phase detector controls
the VCO so that a stable phase relation between VCO and the input signal is achieved. The VCO is running at double the I.F.
frequency with the reference signal for the demodulator obtained by means of a frequency divider circuit.
2
The AFC output is obtained by using the VCO control voltage of the PLL and can be read via the I C bus. The AGC detector
operates on top sync and top white level. The time constant on the AGC system during positive modulation is long to avoid visible
variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included which detects whether the
AGC detector is activated every frame period. When during 3 field periods no action is detected the speed of the system is
increased. For signals without peak white information the system switches automatically to a gated black level AGC. Because a
black level clamp pulse is required for this way of operation the circuit will only switch to black level AGC in the internal mode.
The circuit contains a video identification circuit which is independent of the synchronisation circuit. Therefore search tuning is
possible when the display section of the receiver is used as a monitor.
CHROMA & LUMA PROCESSING.
The I.C. contains a chrominance bandpass filter , the SECAM cloche and chrominance traps. The filters are calibrated using the
tuning frequency and the crystal frequency of the colour decoder. The luminance output signal which is derived from the incoming
CVBS or Y/C signal can be varied in amplitude by means of a separate gain control.
COLOUR DECODING.
The colour decoder can decode PAL, NTSC and SECAM signals. The PAL / NTSC decoder contains an alignment free crystal
o
oscillator with 4 separate pins, a killer circuit and two colour difference demodulators. The 90 phase shift for the reference signal is
made internally. Because it is possible to connect 4 different crystals to the colour decoder, all colour standards can be decoded
without external switching circuits. Crystals not used must be left open. The horizontal oscillator is calibrated by means of the crystal
frequency of the PLL.
The I.C. contains an automatic colour limiting circuit which is switchable which prevents over saturation when signals with a high
chroma-to-burst ratio are received. The acl circuit is designed such that it only reduces the chroma signal and not the burst. This has
the advantage that the colour sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, the 4.43MHz sub-carrier frequency
which is obtained from the crystal oscillator which is used to tune the PLL to the desired free running frequency and the bandgap
reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking
period, when the I.C. is in search or SECAM mode. The base-band delay line is integrated into the package.
14