Hitachi CL32W30TAN Wartungshandbuch Seite 50

JTAG TESTING
A port has been designed into the PCB to allow full JTAG testing of some of the devices. This covers:
•
CPU/Demux
•
CI chips A and B
•
External DRAM controller (not used at present)
•
IEEE1394 Link Layer Controller (not used at present)
There are five lines associated with the JTAG communication. These are:
•
TDIdata into the chip
•
TDOdata out of the chip (return path)
•
TMStest mode select
•
TCKclock line to pass the data chain through the devices
•
TRSTtest mode reset, not used by all devices.
The first 4 of these are used by all the chips, and the reset by the CPU/demux and IEEE1394 only.
It is possible to use JTAG test methods for much of the completed MPEG PCB. JTAG, also known as boundary scan testing, is a
method of loading test bit streams into chips in serial mode using a test mode clock synchronised to the data through a dedicated
port to force I/O pins into known states so that the effect can be read back. For this a test mode must be selected on the chip.
Access to and functionality of the DRAM and flash memory associated with the CPU can be tested using this method, and code can
be downloaded to the flash memory chips. This is made more efficient by the use of the CPU R/NW line to reduce the number of
cycles required to execute a read and write to the devices.
The serial bus is structured in 2 parts, one for the CPU/demux only and the second for all the other devices, this enables a more
efficient flash chip download through the JTAG link since the chain is shorter. Zero ohm resistors link options are placed to connect
the 2 loops together to all the chips in series if the JTAG code loading to the flash chip is not needed.
The JTAG test code will need to be modified if chips are to be omitted from the loops.
The net names used on the diagram attached are as we have used on the schematics, and the programming connector is 14 ways,
carrying 3 grounds. Omitted from the diagram are 10k pull ups on the following lines :-
R271 TDI_CPU
R272 TMS_CPU
R273 TRST_CPU
R274 TDI_CI_DRAMC_LLC
R276 TMS_CI_DRAMC_LLC
with a clock termination network fitted, consisting of 68R and 100pF in series to ground on the following :-
R274/C261 TCK_CPU
R277/C262 TCK_CI_DRAMC_LLC
The facility is connected such that it can be configured as a single loop through all the devices sequentially, with links R263, R264
and R265 fittted, or as two loops, covering the CPU/demux only in one loop and the other ICs in another. Resistors R412, R633 and
R700 are fitted only if the associated chip is omitted.
49