Hitachi CL32W30TAN Wartungshandbuch Seite 31

EXTERNAL 10 BIT ADC (IC803)
The option of using a 10 bit ADC external to the tuner is designed into the PCB, but is not currently used. This uses R781 R823,
R824, R825, R826, R827, R828, R831, R832, C824, C825, C826, C827, C828, C830, C831, C832, C834, C835, C836, C837, C840
and IC803. If this IC is not fitted then all the other components listed here should also be omitted from the PCB.
Link resistors R884 – R889, R860 and R869, R799 should be omitted if this IC is fitted.
EXTERNAL OSCILLATOR CIRCUIT
It may be a future requirement to use an oscillator external to the tuner module. This is accommodated on the PCB using R797,
R807 - R809, R811 – R817, R821, R822, C812 – C818, C820, C822, crystal X800, varicap diode D801, and Q800. This is not
currently used.
The circuit is a discrete Colpitt's style crystal oscillator using the feedback from the COFDM IC to control the frequency by varying
the capacitance of the varicap diode D801. C822, R821, R822 are used to pre-bias the output for the Oscillator buffer needed
(IC800). See the section following.
AFC FEEDBACK AMPLIFIER OPTION (IC816)
An option has been on the PCB to provide an AFC voltage with more range to control the external oscillator if this is needed. This is
currently not used.
It consists of a dual op-amp configured to give a gain of 10 times with an inversion, and a possible output swing of 30V. A following
stage is added to give a further inversion with unity gain. This is made up of R833, R834, R835, R836, R837, R838, R842, C840,
IC816
Bypass links are provided across both sections by R841 (second section only) and R859 (both sections).
CLOCK BUFFERING AND GATING CIRCUIT (IC800)
This stage may be configured in one of three ways:
•
With the oscillator internal to the tuner (currently populated option) it is not normally needed, and bypass resistors
R829, R830 should be fitted instead.
•
In order to correct a problem on some earlier PCBs it is used as a clock gating circuit, with the function of resetting the
PLL in the COFDM IC under some startup conditions. The control is automatically provided by a control line direct from
the MPEG CPU. For this option R830 should be omitted.
•
In the case where the external oscillator is used it is needed as a buffer to convert low level analogue clock to a TTL level.
In this case the PLL reset function is also available. R830 and R829 should be omitted and R797 fitted for this option.
COFDM DECODER (IC801 / L64780)
Using the 18.288MHz clock the 8 bit signal is decoded by the LSI chip (IC801) on the PCB to produce a parallel transport stream.
The clock input is fed to the COFDM IC through a 47R resistor (R810), this provides some waveform shaping and buffering between
the 5V TTL driver and the 3.3V LSI silicon.
The on-chip PLL reset pin (TEST0) is reset directly from the MPEG CPU while the main chip reset is delayed to both COFDM and
FEC ICs through R784, C772. This is done to force the COFDM IC to start up correctly reliably. Also a capacitor (C770) is fitted on
the JTAG reset pin to ensure that the COFDM chip always powers up correctly.
The control for the IF AGC is generated within the L64780 as a sigma-delta output which is filtered by R868, R795, C811. The
COFDM IC also supplies the AFC signal to the tuner VCXO, again using a filtered (R796, R847, C842, , (C841)) sigma-delta output
format.
The control (initialisation, sending of commands and reading of status) is done through the I2C bus from the MPEG CPU carried on
PL801. The serial control mode is selected by pulling the 'S_P' pin high through R863, with the I2C data driven from the LSB of the
data I/O port, the remainder of the data port is used to set the I2C address which is called up during initialisation. R867, R866 are
the bus pull-ups, R864, R865 the series resistors and C870 is added on the data line correct the bus timing.
The enable control signal for the tuner I2C is provided through one port pin on this chip, it is enabled by an I2C command before
each tuner command and disabled immediately afterwards.
The L64780 contains an 8 bit ADC which can be used as an alternative to the ADC in the tuner module or the external 10 bit ADC.
The input interface components associated with this are R870, R871, R872, R873, R874, R875, C846, C847.
The L64780 contains an internal 'x3' PLL controlled oscillator generating a 54.864MHz signal locked to the incoming 18.288MHz
signal. This clock is provided with the data to the FEC (L64724). The local PLL power supply is filtered through R861 and C843, and
the associated PLL components are R862, C844 and C845.
The chip contains a JTAG test port which is brought out to connector PL800, with termination components R839, R840, R849,
R850, C839 to maintain the correct conditions on these pins.
The digital signal is fed to the FFT section of the L64780 COFDM decoder IC. This derives the pilot tone signals, which can be used
in conjunction with the information programmed by the MPEG CPU to decode the incoming data using an FFT algorithm into a set of
I/Q quadrature signals. These are each 3 bit resolution and provide the signals for the FEC. The IC also provides information about
the signal quality which is read back from the chip registers through the I2C bus in a form to be used in the menus for the user and
for servicing and testing.
54MHZ CLOCK BUFFER STAGE
This is needed only when a L64780 version A chips is used, it's function is to correct the 54MHz clock drive level to the FEC. When
L64780 version B (onward) chips are used the stage is by-passed by R846. The stage is made up of IC817, C775, C776, R820
in a self biasing mode, with provision for input biasing as R793, R794.
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