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ADDRESS DECODER
The 80C196 address decoding is controlled by an EP320 EPLD (U7). Two different
decoding is possible, depending on the state of the signal PIB (OPT2). In the module
mode, PIB is high. When the NIBP module is plugged into the ACCUTORR 3/4, PIB is
pulled low, and a different set of decoding is activated.
50031
INPUTS
BANK — | 1
20|— Ves
.
Al2
2
1 一 PUMP
Name
Pin
A13
3
18
PIB
BANK*
1
¡active low, bank select (1-> ROM;0-> shadow RAM)
A14
4
17
RST*
A12
2
¡active high, 800195 address bit 12 (not used)
A15
5
16
EXT*
A13
3
¡active high, 800196 address bit 13
ΑΟΝ
6
15)
RDY*
A14
4
¡active high, 800198 address bit 14
РМР—
7
14|—— ROM*
AIS
5
şactive high, 800196 address bit 15
OVPR—İg
13|- DAC*
ADV*
6
¡active low, 800198 address sirobe
PORSTS|
9
人 一 一 RAM
PMP
7
active high, pump control input
GND——|
10
11}-—— WR*
OVPR
8
¡active high, overpressure signal
o
PORST*
9
¡active low, power-on reset
WR*
11
jactive low, 80196 write signal
PIB
18
sactiva high, PIB mode (1-> module;0-
> DSBP)
OUTPUTS
Name © Fin
RAM*
12
sactive low, RAM decode enable
DAC*
13
active low, DAC decode enable
ROM*
14
jactive low, local ROM decode enable
RDY
15
sactive high, ready signal to 80196
EXT*
16
yactive low, external peripherals decode enable
RST*
17
active low, reset signal to 80196
PUMP
19
active high, purnp control output
FIGURE
1-7
U7 NIBP Control Board:
DECODE4:
Address Decoder
in the module mode, (module mode = DSBP module used in any product other than
ACCUTORR 3/4) when the bank bit BANK, (US pin 33) is set high, the lower 32K bytes
(0-32K) are mapped to the on-board EPROM; the next 8K bytes (32K-40K) are
mapped to non-volatile RAM; the next 16K bytes (40K-56K) are not used; and the last
8K bytes (66K-64K) are mapped to I/O, the only 1/0 available being the quad DAC, US.
When the bank bit is set low, the lower 8K bytes (OK-8K) are still mapped to the on-
board EPROM; but the next 24K (8K-32K) bytes are mapped to non-volatile RAM; the
remaining RAM and 1/0 space remain the same.
In the stand-alone mode, (stand-alone mode is when the DSBP module is used in the
ACCUTORR 3/4) when the bank bit BANK is set high, the lower 32K bytes (QK-32K)
are mapped to the oif-board Datasette; the next 24K bytes (82K-56K) are mapped to
non-volatile RAM; the last 8K bytes (56K-64K) are mapped to off-board peripherals.
When the bank bit is set low, the lower 8K bytes (OK-8K) are still mapped to the off-
board EPROM; the next 24K bytes (8K-32K) are mapped to non-volatile RAM; the next
8K bytes (82K-40K) remains mapped to non-volatile RAM; the next 16K bytes (40K-
56K) are not used; and the last 8K bytes (56K-64K) remains mapped to off-board
peripherals.
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1-50
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