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Sa02 Processor
The 63BO9E, U16, is running at 1.3824MHz. The E and G clocks to the 63B09E (at
1.382MHz) are generated by dividing by 4 the 5.5296MHz system clock of the 80C196
processor (divide by 2 from the 11.0592MHz crystal). The program and data memory
far the 63BO9E is the same vídeo memory used by the LCD controller. The memory is
shared by using the TSC (tri-state control) signal of the 63BO9E. Thus the 63B09E ad-
dress and data buses are used only half the time for the processor itself, without affect-
ing the operation of the processor.
The decoding for the 63B09E processor is performed by U6, an EP600 EPLD. RAM
occupies the top 32K byte (32K-64K) of the address space. The bottom 4K of this 32K
bytes of RAM (32K-36K) is allocated as LCD video memory. This 32K RAM is ac-
cessed by the main control processor as eight pages of 4K memory. The paging is
controlled by the three page bits in the control register, PGO, 1, and 2. For example,
PG2,1,0=000 accesses the video memory (82K-36K); PG2,1,0=111
accesses the
highest 4K bytes in the 63B09E address space (60K-64K).
EP600
~
INPUTS
E
1
2a— Ve
Name
Pin
MA1 -一 一 |2
23 | 一 一 MAO
SWF —+ 3
22 |—— INT*
E
1
spositive trigger, E clock to be divided down
NIC
4
21 |+—-APTO*
ΜΑΙ
2
¡active high, 6809 address bus bit 1
CPX
5
20 APT1*
SWR*
3
¡active low, 6809 write signal
NIC
6
19 | 一 一 APT2*
MA2
11
jactive high, 6809 address bus bit 2
N/C
7
18 — SRAM*
MA15
14
jactive high, 6809 address bus bit 15
N/C
8
17 |— COMP*
INTF*
16
zactive low, interference input from analog board
NG
9
16 |—— INTF*
GOMP*
17
¡active low, comparator input from analog board
NIG
40
15 | RDO
MAO
23
¡activa high, 6809 address but bit O
MA2
11
14 ドー MAIS
GND
12
13 一 一 NMC
TTT
OUTPUTS
Name
Pin
CPX
5
¡clock signal to analog board (E divide by 22)
RDO
15
jactive high, 6809 data bus bit 0
SRAM*
18
¡active low, group decode for 6809 RAM
APT2*
19
jactive low, analog board strobe 2
APT1*
20
jactive low, analog board strobe 1
APTO*
21
jactive low, analog board strobe 0
INTE
22
¡active low, interrupt signal to NIBP processor
FIGURE 1-4
U9 Interface Board:
SaO。:
SaO。 Decoder
Three strobes for the Sa02 analog board are generated, APTO, 1, and 2. These three
strobes are used to clock data and control signals to the A/D system in the Sa02
analog board. Two input bits from the Sa02 analog board, INTF*, (active low when
there is interference from the sensor) and COMP*, (the active low comparator output
signal) can also be read via data bus bit 0, RDO. it also generates the 62.84 KHz.to the
Sa02 analog board by dividing the processor clock, E, by 22.
1-43
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