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Verfügbare Sprachen
Verfügbare Sprachen
LCD Controller
U14, MSM6255, is a LCD controller that generates all the timing signals for the LCD
(128x240 pixels). These include: FR, the frame signal to the LCD that is active once
every frame of the display; LO, the line signal to the LCD that is active once every
scan line of the display; DF, the alternate frame signal needed to drive the LCD; and
CP, the clock to the LCD. It also takes data from the video RAM, U13, and shifts it out
to the LCD four bits at a time via UDO, UD1, UD2, and UD3. The video RAM is imple-
mented by a 32K by 8 static RAM as a triple-ported RAM. It is being transparently
shared by the main contro! processor in the NIBP module, a 80C196, the LCD control-
ler itself, and the supplemental SaO2 processor, U16, a 63BO9E. Since the LCD
screen only requires 4K of RAM. The rest is used by the 68BOSE for its program and
data storage. Program for the 68BO9E is directly loaded by the main control proces-
sor. Communication between the main control processor and the SaO2 processor is
also done via the triple ported RAM. This architecture allows efficient access between
the two processors. lt also allows each processor to access the display memory inde-
pendentiy and without interference to the display process.
The multiplexing of the addresses between the three possible sources for the triple-
ported RAM is done via the LCD controller. The multiplexing of the data buses is done
by U15, a 74HCT245, and U12, an EP600 EPLD. U12 is implemented as a bidirection-
al registered transceiver. The LCD controller timing is generated by U7, another
EP600 EPLD.
EP60O
INPUTS
BCLK -一 -| 1
24 |—— Veo
.
BWR*—|
z
23|
一 cHo
Name
Pin
SWR*—-|3
22|——RYD
BCLK
1
ipositive trigger, 5.5296MHz clock from B0196 processor
CHOD—|4
21 ーー+TSC
BWR*
2
sactive low, 80196 write signal
CPX——|5
+ .
20/—DIEN
SWR*
3
iactive low, 6809 write signal
SVRAME.| 6
， 扫 | —
ED"
SRAM*
6
¡active low, 6809 RAM decode enable
ADV? —
7
18| 一 一 ADFx*
ADV*
7
¡active low, 80196 address strobe
Si——
8
17 |—VAWR*
BRD*
11
¡active low, 80196 read signal
E
9
16|—-VROE*
BCLK
13
ipositive trigger, inverse of BCLK
Q
10
15 |-—-VRCE*
VRAM*
14
active low, 80196 video RAM enable
ВАО*— | 11
14 | VRAM*
CHO
23
active high, character clock strobe from LCD controller
GND.
12
13 |—BCLK*
一
一 一 一
OUTPUTS
Name
Pin
CHOD
4
sactive high, delayed CHOD, not used
CPX
5
active high, analog ciock, not used
51
8
sactive high, clock to LCD controller
E
9
iactive high, E clock to 6809
a
10
ractive high, Q clock to 6809
VRCE*
15
sactive low, video RAM chip enable
VROE*
16
¡active low, video RAM output enable
VAWR*
17
;active low, video RAM write signal ©
>
ADF*
18
iactive low, address floating to LCD, not used
ED*
19
¡active low, E delayed, not used
DIEN
20
¡active high, display enable to LCD controller
TSG
21
sactive high, tri-state control to 6309
RDY
22
sactive high, ready signal to 80196
FIGURE 1-2
U7 Interface Board:
LCDCON:
LCD Controller
1-41
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