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Verfügbare Sprachen
The Recorder Registers
The recorder head and motor registers U8, controls the recorder thermal print head
and the paper movement motors in the recorder. They are located on the recorder
board (US and U5 respectively).
The Tone Register
The tone register, U9, is implemented with a EP600 EPLD. The 124 KHz clock, CPX, is
- divided down by a constant determined by a five bit constant that is being written into
the lower order five bits of the tone register. The output of the frequency divider,
FREQ*, is fed to the audio amplifier.
Name
Fin
DBO
PEL
DBz
pB3
DB4
DES
DEE
D87
¡active high, 80C196 processor data bus bit O
jactive high, 806196 processor data bus bit 1
¡activa high, 800186 processor deta bus bit 2
¡active high, 800186 processor data bus bit 3
¡activo high, 800196 processor data bus bit 4
¡active high, BOC 195 processor deta bus bit 8
sactive high, 800196 processor dala bus bit 6
jactive high, 80C198 processor dala bus bit 7
FIGURE 1-5
US Interface Board: TONE: Tone Generator
The Datasette Connector
The Datasette connector, 412, is used to connect the 1 megabit EPROM on the
Datasette to the main control processor. When the NIBP module is connected to the
motherboard, the memory decoder in the module automatically disables the on board
EPROM and let the external Datasette memory takes control. (This is done by ground-
ing the PiB signal on the 50 pin NIBP cable.) In addition, the wait state generator and
the guad dac decoding strobe, DAC*, on the interface board takes precedence over
those generated in the module.
The 1 megabit EPROM on the Datasette is organized into four pages of 32K bytes
ROM, controlled by the page bits PG3 and PG4. On power-up, page 0 is selected.
Page 0 contains initialization and SaO2 code to be downloaded; page 1 contains ser-
vice diagnostic and configuration code; page 2 and page 3 contains normal operating
code the main control processor, the 800196, operates in.
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