Ssi Timing And Transmission - TR-Electronic _LLB500(F)-00601 Benutzerhandbuch

8.8.2 SSI Timing and Transmission

Figure 21: SSI timing diagram
Declaration of the abbreviations:
Abbreviation Declaration
Transfer timeout (Monoflop time):
It is the minimum time required by the slave to realize that the data
t
m
transmission is complete. After tm, the data line goes to idle state and the slave
starts updating its data in the shift register.
Pause time:
t
p
It is the time delay between two consecutive clock sequences from the master.
The SSI is initially in the idle mode, where the data and clock lines stay "HIGH"
updating its internal value.
The transmission mode is evoked when the master initiates a sequence by pulling the clock line to
"LOW". Once, the slave receives the resulting falling edge
stops updating its internal value. With the first rising edge
value is transmitted and with consequent rising edges, the data bits are sequentially transmitted.
After the transmission of the complete data word
edge of the clock sets the clock line to "HIGH". The slave sets or leaves the data line to "LOW" and
remains there for the time (t
(data-output request) is received within the time (t
(multiple transmissions).
If there were no clock pulses within time tm, the slave starts updating its internal value after setting the
data line to "HIGH" (idle mode). This marks the end of a single transmission of a data word. Once the
slave receives a clock signal at a time (t
transmission of the new value begins as described earlier.
Printed in the Federal Republic of Germany
03/09/2016
), to recognize the transfer timeout. If a falling edge of the clock signal
m
), the same data as before will be transmitted again
m
) (> = t
p
TR - ELE - BA - DGB - 0021 - 06
at the clock signal line, it automatically
of the clock line, the MSB of the sensor's
(e.g. LSB is transmitted) an additional last rising
) the updated position value is frozen and the
m
and the slave keeps
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