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6-3. Signal timing

The timing charts shown below are for the P1 type counter board. The high level and low
level logic are reversed for the P2 type. Also, the overall reset (pin 1), overall start (pin 2)
and overall Go/No Go output (pin 3) timings for I/O 1 and I/O 2 of the display unit are the
same for both the P1 and P2 type counter boards.
2!§Start / 1!∞Reset input
9 to !¡, @£ to @∞Result evaluation output
Note
When the start/hold terminal 2!§'s initial setting is
Go result and the display.
Go/No Go output
and display value.
67, @º@¡ Comparator value setting 45, !•!ª mode switching input
I N
MIN. 5 ms MIN. 4 ms
Sampling 6 ms
2 !§
MAX. 6 ms
I N
DATA (OUT)
MAX. 50 ms
the ON signal will hold the Go/No
33

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