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7.5.3
LBU Read zum ERTEC200 mit gemeinsamer Read-/Writeleitung (Ready low aktiv)
LBU_CS_R_N/
LBU_CS_M_N
LBU_WR_N
LBU_A(20:0)/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
LBU_RDY_N
LBU_D(15:0)
Abbildung 15: LBU-Read-Sequenz bei gemeinsamer RD-/WR-Leitung
Parameter
t
write signal deasserted to chip select asserted setup time
WCS
t
address valid to chip select asserted setup time
ACS
t
chip select asserted to ready enabled delay
CRE
t
chip select asserted to data enable delay
CDE
t
ready active pulse width
RAP
t
ready asserted to data valid delay
RTD
t
write signal inactive to chip select deasserted hold time
CWH
t
address valid to chip select deasserted hold time
RAH
t
data valid/enabled to chip select deasserted hold time
RDH
t
read recovery time
RR
Tabelle 27: Timing für LBU-Readzugriffe mit gemeinsamer Read-/Writeleitung
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Änderungen vorbehalten
t
WCS
t
ACS
t
CRE
t
CDE
Description
t
RAP
t
RTD
80
t
RR
t
CWH
t
CAH
t
CDH
Min
Max
2 ns
0 ns
5 ns
12 ns
5 ns
12 ns
17 ns
23 ns
5 ns
0 ns
0 ns
0 ns
12 ns
25 ns
ERTEC 200 Handbuch
Version 1.1.2
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