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4.5.2
Watchdog-Timer 1 .................................................................................................................................44
4.5.3
Watchdog-Interrupt................................................................................................................................44
4.5.4
WDOUT0_N ..........................................................................................................................................44
4.5.5
WDOUT1_N ..........................................................................................................................................44
4.5.6
Watchdog-Register................................................................................................................................45
4.5.7
Adressbelegung Watchdog-Register .....................................................................................................45
4.5.8
Watchdog-Register Beschreibung .........................................................................................................45
4.6 UART-Schnittstelle.........................................................................................................................................47
4.6.1
Adressbelegung UART-Register ...........................................................................................................48
4.6.2
UART-Register Beschreibung ...............................................................................................................49
4.7 Synchrones Interface SPI ..............................................................................................................................53
4.7.1
Adressbelegung SPI-Register ...............................................................................................................54
4.7.2
SPI-Register Beschreibung ...................................................................................................................55
4.8 System-Control-Register................................................................................................................................57
4.8.1
Adressbelegung System-Control-Register ............................................................................................57
4.8.2
System-Control-Register Beschreibung ................................................................................................58
5
Allgemeine Hardware Funktionen .............................................................................................. 63
5.1 Takterzeugung und Taktversorgung ..............................................................................................................63
5.1.1
Taktversorgung im ERTEC 200.............................................................................................................63
5.1.2
Taktversorgung JTAG ...........................................................................................................................64
5.1.3
Taktversorgung PHYs und Ethernet-MACs ...........................................................................................64
5.2 Resetlogik des ERTEC 200 ...........................................................................................................................65
5.2.1
PowerOn-Reset .....................................................................................................................................65
5.2.2
Hardware-Reset ....................................................................................................................................66
5.2.3
Watchdog-Reset....................................................................................................................................66
5.2.4
Software-Reset......................................................................................................................................66
5.2.5
IRT-Switch-Reset ..................................................................................................................................66
5.3 Adressraum- und Quittungsverzug- Überwachung ........................................................................................67
5.3.1
AHB-Bus Überwachung.........................................................................................................................67
5.3.2
APB-Bus Überwachung.........................................................................................................................67
5.3.3
EMIF Überwachung...............................................................................................................................67
5.4 Konfigurationsmöglichkeiten am ERTEC 200 ................................................................................................67
6
External Memory Interface (EMIF) .............................................................................................. 69
6.1 Adressbelegung EMIF-Register .....................................................................................................................70
6.2 EMIF-Register Beschreibung .........................................................................................................................70
7
Local Bus Unit (LBU).................................................................................................................... 74
7.1 Page-Range-Einstellung ................................................................................................................................75
7.2 Page-Offset-Einstellung .................................................................................................................................75
7.3 LBU-Adressmapping......................................................................................................................................76
7.4 Page-Control-Einstellung ...............................................................................................................................77
7.5 Host-Zugriffe auf den ERTEC 200 .................................................................................................................77
7.5.1
LBU Read zum ERTEC200 mit separater Read-/Writeleitung (Ready low aktiv) ..................................78
7.5.2
LBU Write zum ERTEC200 mit separater Read-/Writeleitung (Ready low aktiv)...................................79
7.5.3
LBU Read zum ERTEC200 mit gemeinsamer Read-/Writeleitung (Ready low aktiv)............................80
7.5.4
LBU Write zum ERTEC200 mit gemeinsamer Read-/Writeleitung (Ready low aktiv) ............................81
7.6 Host Interrupt Handling ..................................................................................................................................81
7.7 Adressbelegung LBU-Register.......................................................................................................................82
7.8 LBU-Register Beschreibung...........................................................................................................................82
8
DMA-Controller ............................................................................................................................. 84
8.1 Adressbelegung DMA-Register......................................................................................................................85
8.2 DMA-Register Beschreibung..........................................................................................................................85
9
Multiport Ethernet PHY ................................................................................................................ 87
10
Speicherbeschreibung................................................................................................................. 90
10.1 Speicheraufteilung des ERTEC 200 ..............................................................................................................90
10.2 Detaillierte Speicherbeschreibung .................................................................................................................91
11
Test und Debugging..................................................................................................................... 93
11.1 Embedded Trace Macrocell ETM9................................................................................................................93
11.1.1 Tracemodi..............................................................................................................................................93
11.1.2 Features des ETM9-Modul ....................................................................................................................93
11.1.3 ETM9 - Register....................................................................................................................................93
11.2 Trace - Interface............................................................................................................................................94
11.3 JTAG - Schnittstelle ......................................................................................................................................94
11.4 Debugging über UART...................................................................................................................................94
12
Sonstiges ...................................................................................................................................... 95
12.1 Abkürzungen/ Begriffsverzeichnis:.................................................................................................................95
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6
ERTEC 200 Handbuch
Version 1.1.2
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