Inhaltsverzeichnis - Siemens ERTEC 200 Handbuch

Inhaltsverzeichnis

1 Einleitung ...................................................................................................................................... 8
1.1 Einsatzgebiete des ERTEC 200.....................................................................................................................8
1.2 Features des ERTEC 200..............................................................................................................................8
1.3 Aufbau des ERTEC 200.................................................................................................................................9
1.4 Gehäuse des ERTEC 200..............................................................................................................................10
1.5 Signal-Funktions-Beschreibung .....................................................................................................................11
1.5.1 GPIO 0-31 und alternative Funktionen ..................................................................................................11
1.5.2 JTAG und Debug...................................................................................................................................12
1.5.3 Trace-Port..............................................................................................................................................12
1.5.4 Clock und Reset ....................................................................................................................................13
1.5.5 Test-Pins ...............................................................................................................................................13
1.5.6 EMIF (External Memory Interface).........................................................................................................13
1.5.7 LBU, MII-Interface oder ETM-Trace-Interface .......................................................................................15
1.5.8 Ethernet PHY1 und PHY2 .....................................................................................................................17
1.5.9 Stromversorgung ...................................................................................................................................18
2 ARM946E-S Prozessor ................................................................................................................. 20
2.1 Aufbau des ARM946E-S................................................................................................................................20
2.2 Beschreibung des ARM946E-S .....................................................................................................................21
2.3 Arbeitsfrequenz des ARM946E-S ..................................................................................................................21
2.4 Cache-Struktur des ARM946E-S ...................................................................................................................21
2.5 Tightly Coupled Memory (TCM) .....................................................................................................................21
2.6 Memory Protection Unit (MPU) ......................................................................................................................22
2.7 Bus-Interface des ARM946E-S ......................................................................................................................22
2.8 ARM946E-S Embedded Trace Macrocell (ETM9) .........................................................................................22
2.9 ARM-Interrupt-Controller (ICU) ......................................................................................................................22
2.9.1 Priorisierung der Interrupts ....................................................................................................................23
2.9.2 Triggermodi ...........................................................................................................................................23
2.9.3 Maskierung der Interrupt-Eingänge .......................................................................................................23
2.9.4 Software-Interrupts für IRQ....................................................................................................................23
2.9.5 Nested Interrupt Struktur .......................................................................................................................23
2.9.6 EOI End-Of-Interrupt ............................................................................................................................23
2.9.7 IRQ-Interrupt-Quellen ............................................................................................................................24
2.9.8 FIQ-Interrupt-Quellen ............................................................................................................................24
2.9.9 IRQ-Interrupts als FIQ-Interrupt-Quellen ...............................................................................................25
2.9.10 Interrupt-Control-Register......................................................................................................................25
2.9.11 ICU-Register Beschreibung...................................................................................................................26
2.10 ARM946E-S - Register ..................................................................................................................................30
3 Bussystem des ERTEC 200......................................................................................................... 31
3.1 Kommunikationsbus „Multi-Layer AHB" .........................................................................................................31
3.1.1 AHB-Arbiter ...........................................................................................................................................31
3.1.2 AHB-Master-Slave-Kopplung.................................................................................................................31
3.2 Peripheriebus APB.........................................................................................................................................31
4 Peripherie am APB-Bus ............................................................................................................... 32
4.1 BOOT-ROM ...................................................................................................................................................32
4.1.1 Booten von externem ROM ...................................................................................................................33
4.1.2 Booten über SPI ....................................................................................................................................33
4.1.3 Booten über UART ................................................................................................................................33
4.1.4 Booten über LBU ...................................................................................................................................33
4.1.5 Memory-Swapping.................................................................................................................................33
4.2 General Purpose IO (GPIO)...........................................................................................................................34
4.2.1 Adressbelegung GPIO-Register ............................................................................................................35
4.2.2 GPIO-Register Beschreibung ................................................................................................................35
4.3 Timer 0/1/2.....................................................................................................................................................37
4.3.1 Timer 0 und 1 ........................................................................................................................................37
4.3.1.1 Timer 0/1 - Interrupts.......................................................................................................................38
4.3.1.2 Timer 0/1 - Vorteiler ........................................................................................................................38
4.3.1.3 Kaskadierung der Timer 0/1.............................................................................................................38
4.3.2 Timer 2 ..................................................................................................................................................38
4.3.3 Adressbelegung Timer-Register ............................................................................................................39
4.3.4 Timer-Register Beschreibung ................................................................................................................39
4.4 F - Timer Funktion.........................................................................................................................................42
4.4.1 Adressbelegung F-Timer-Register.........................................................................................................43
4.4.2 F-Timer-Register Beschreibung.............................................................................................................43
4.5 Watchdog-Timer ............................................................................................................................................44
4.5.1 Watchdog-Timer 0 .................................................................................................................................44
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ERTEC 200 Handbuch
Version 1.1.2