Clock Und Reset; Test-Pins; Emif (External Memory Interface) - Siemens ERTEC 200 Handbuch

1.5.4

Clock und Reset

Nr. Signalname
42 CLKP_A
43 CLKP_B
44 F_CLK
45 REF_CLK
46 RESET_N
1.5.5

Test-Pins

Nr. Signalname
47 TEST_N (3)
48 TMC1 (3)
49 TMC2 (3)
50 TACT_N (3)
1.5.6

EMIF (External Memory Interface)

Nr. Signalname
51 DTR_N
52 OE_DRIVER_N
53 A0
54 A1
55 A2
56 A3
57 A4
58 A5
59 A6
60 A7
61 A8
62 A9
63 A10
64 A11
65 A12
Copyright © Siemens AG 2010. All rights reserved.
Änderungen vorbehalten
IO Pull- PIN-
(Reset) Nr.
CLOCK- / RESET-ERZEUGUNG
I (I) B14
O D14
I (I) B13
Abhängig
vom PIN A15
CONFIG[1]
I (I) up B7
IO Pull- PIN-
(Reset) Nr.
TEST
I (I) up T5
I (I) G5
I (I) H6
I (I) dn J5
Alternative IO
Reset-Funktion (Reset)
EMIF (External Memory Interface)
BOOT0 B (I)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
Bemerkung
Quarz-Anschluss
Quarz-Anschluss
F_CLK für F-Counter
Tristate oder
Referenztakt Ausgang 25 MHz
PowerOn-Reset
Bemerkung
Testmode
Testkonfiguration
Testkonfiguration
TESTACT-TAP-Reset
Pull- PIN- Bemerkung
Nr.
Direction Signal für externen
Treiber oder Scan Clock (Scan
up E7 Mode)
ERTEC 200 - Bootmode (event.
Ext. PD nötig)
Enable Signal für externen Treiber
D8
oder Scan Clock (Scan Mode)
Adress-Bit 0
B4
SDRAM: Bank-Adress 0
Adress-Bit 1
A3
SDRAM: Bank-Adress 1
Adress-Bit 2
B3
SDRAM: Adress 0
Adress-Bit 3
B2
SDRAM: Adress 1
Adress-Bit 4
D4
SDRAM: Adress 2
Adress-Bit 5
C2
SDRAM: Adress 3
Adress-Bit 6
C1
SDRAM: Adress 4
Adress-Bit 7
D2
SDRAM: Adress 5
Adress-Bit 8
D1
SDRAM: Adress 6
Adress-Bit 9
E2
SDRAM: Adress 7
Adress-Bit 10
E1
SDRAM: Adress 8
Adress-Bit 11
F2
SDRAM: Adress 9
Adress-Bit 12
F1
SDRAM: Adress 10
13
ERTEC 200 Handbuch
Version 1.1.2