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7.5.2
LBU Write zum ERTEC200 mit separater Read-/Writeleitung (Ready low aktiv)
LBU_CS_R_N/
LBU_CD_M_N
LBU_WR_N
LBU_A(20:0)/
LBU_SEG(1:0)
LBU_BE(1:0)_N
LBU_RDY_N
LBU_D(15:0)
Abbildung 14: LBU-Write-Sequenz bei separater RD-/WR-Leitung
Parameter
t
chip select asserted to write pulse asserted delay
CSWS
t
address valid to write pulse asserted setup time
AWS
t
write pulse asserted to ready enabled delay
WRE
t
write pulse asserted to data valid delay
WDV
t
ready active pulse width
RAP
t
write pulse deasserted to chip select deasserted delay
WCSH
t
address valid to write pulse deasserted hold time
WAH
t
ready asserted to write pulse deasserted delay
RTW
t
data valid/enabled to read pulse deasserted hold time
WDH
t
write recovery time
WR
Tabelle 26: Timing für LBU-Schreibzugriffe mit separater Read-/Writeleitung
Copyright © Siemens AG 2010. All rights reserved.
Änderungen vorbehalten
t
CSWS
t
AWS
t
WRE
t
WDV
Description
t
RTW
t
RAP
Min
0 ns
0 ns
5 ns
17 ns
0 ns
0 ns
0 ns
0 ns
25 ns
79
t
WCSH
t
WR
t
WAH
t
WDH
Max
12 ns
40 ns
23 ns
ERTEC 200 Handbuch
Version 1.1.2
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