Cpu Configuration Submenu; Chipset Configuration Submenu - DLoG IPC 7 Handbuch

22.5.4. CPU Configuration Submenu

Feature
Processor Info
Block
On Demand
Clock
Modulation

22.5.5. Chipset Configuration Submenu

Feature
Memory Hole
IOAPIC
APIC ACPI SCI
IRQ
C4 On C3
Active State
Power
Management
PCI Express
Port 1
DLoG IPC 7/215
Options Description
No option Displays the processor manufacturer, brand,
frequency, and cache sizes.
Disable Allows a reduction of the performance of the
processor by utilizing clock modulation. The
value indicates the CLOCK ON to CLOCK OFF
interval ratio. E.g. 75% results in a
performance decrease of about 25%.
Note: This option is only available for Celeron
M CPUs
Options Description
Disabled Enable or disable the memory hole between
15MB-16MB 15MB and 16MB. If enabled, accesses to this
range are forwarded to the LPC / PCI bus.
Disabled Enable / Disable ICH6M IOAPIC function.
Enabled
Disabled If set to Disabled IRQ9 is used for the SCI.
Enabled If set to Enabled IRQ20 is used for the SCI.
Disabled If enabled the CPU is put to C4 state, when
Enabled the ACPI OS initiates a transition to C3, for
additional power saving at "Desktop Idle
Mode".
Disabled Enable or disable PCI Express L0s and L1 link
Enabled power states.
Enabled
Disabled
Handbuch
Anhang F: BIOS
179