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STB Status Byte Register
STB is main register where information from other status registers and from output queue is collected.
Value of STB register is reset after switching on the device or after sending command *CLS. This
command reset the STB register except bit MAV, which remains set if the output queue is not empty.
STB register value can be read via serial message or through general query *STB?.
Bit configuration of Status Byte Register:
OSS Operation Summary Status, bit 7. SCPI-defined. The OSS bit is set to 1 when the data in the
OSR (Operation Status Register) contains one or more enabled bits which are true.
RQS Request Service, bit 6. The bit is read as a part of status byte only when serial message is sent.
MSS Master Summary Status, bit 6. The MSS bit is set to 1 whenever bits ESB or MAV are 1 and
enabled (1) in the SRE. This bit can be read using the *STB? command. Its value is derived
from STB and SRE status.
ESB Event Summary Bit, bit 5. His value is derived from STB and SRE status. The ESB bit is set
to 1 when one or more enabled ESR bits are set to 1.
MAV Message Available, bit 4. The MAV bit is set to 1 whenever data is available in the IEEE488
Output Queue (the response on query is ready).
QSS Questionable Summary Status, bit 3. SCPI-defined. The QSS bit is set to 1 when the data in
the QSR (Questionable Status Register) contains one or more enabled bits which are true.
SRE Service Request Enable Register
The Service Request Enable Register suppresses or allows the STB bits. "0" value of a SRE bit
means, that the bit does not influence value of MSS bit. Value of any unmasked STB bit results in
setting of the MSS bit to the level "1" . SRE bit 6 is not influenced and its value is "0". The SRE
register value can be set via the command *SRE followed by mask register value (0 – 191). The
register can be read with the command *SRE?. The register is automatically resets after switching the
device on. The register is not reset by the command *CLS.
ESR Event Status Register
Every bit of the EventStatusRegister corresponds to one event. Bit is set when the event is changed
and it remains set also when the event passed. The ESR is cleared when the power is turned on
(except bit PON which is set), and every time it is read via command *ESR? Or cleared with *CLS.
Bit configuration of Event Status Register:
PON Power On, bit 7. This event bit indicates that an off-to-on transition has occurred in the
device's power supply.
User Request, bit 6. Bit is not used and it is always "0".
URQ
CME Command Error, bit 5. This event bit indicates that an incorrectly formed command or query
has been detected by the instrument.
EXE Execution Error, bit 4. This event bit indicates that the received command cannot be executed,
owing to the device state or the command parameter being out of limits.
DDE Device Dependent Error, bit 3. This event bit indicates that an error has occurred which is
neither a Command Error, a Query Error, nor an Execution Error. A Device-specific Error is
any executed device operation that did not properly complete due to some condition, such as
overload.
QYE Query Error, bit 2. The bit is set if the device is addressed as talker and output queue is empty
or if control unit did not pick up response before sending next query.
OPC Operation Complete, bit 0. This event bit is generated in response to the *OPC command. It
indicates that the device has completed all selected pending operations.
ESE Event Status Enable Register
The Event Status Enable Register allows one or more events in the Event Status Register to be
reflected in the ESB summary-message bit. This register is defined for 8 bits, each corresponding to
Owner's Manual
OCM160 Precision DC Calibrator
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