Aventics AES Serie Systembeschreibung Seite 97

AVENTICS | AES I/O Modules, Analog | R412018147–BAL–001–AG
6.3.4.4 Process data of the inputs for "8 bits direct" data format
Table 34: Structure of the process data of the inputs for "8 bits direct" data format (4AI4M12E)
Bit 7 Bit 6 Bit 5
D7 D6
D: Value of the bit (0/1)
1)
This mode may only be used with settings 0 to 10 V or 0 to 20 mA.
Table 35: Value ranges of the process data for "8 bits direct" data format (4AI4M12E)
Nominal value of the
Resolution
measurement range
0 to 12.75 V 50 mV/bit
0 to 25.50 mA 100 μA/bit
D.. : Value of the bit (0/1)
Bit 4 Bit 3
D5 D4 D3
Value
0.0 V
0.05 V
10.0 V
12.75 V
> 12.75 V
0.0 mA
0.1 mA
20.0 mA
25.5 mA
> 25.5 mA
Structure of the I/O Module Data
1)
Bit 2 Bit 1 Bit 0
D2 D1 D0
Example
D0–D7 D0–D7
Decimal Hexadecimal
0 00
1 01
200 C8
255 FF
255 FF
0 00
1 01
200 C8
255 FF
255 FF
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