Aventics AES Serie Systembeschreibung Seite 95

AVENTICS | AES I/O Modules, Analog | R412018147–BAL–001–AG
6.3.4.2 Process data of the inputs for "8 bits" data format
Table 30: Structure of the process data of the inputs for "8 bits" data format (4AI4M12E)
Bit 7 Bit 6 Bit 5
D7 D6
D: Value of the bit (0/1)
Table 31: Value ranges of the process data for "8 bits" data format (4AI4M12E)
Nominal value of the
Resolution
measurement range
0 to 10 V 40 mV/bit
2 to 10 V 32 mV/bit
to
0 20 mA 80 μA/bit
to
4 20 mA 64 μA/bit
D.. : Value of the bit (0/1)
1)
In this operating mode, monitoring for a wire break is not possible (see "6.2 Diagnostic data" on page 86).
Conversion to the decimal value 1000 can be achieved in the PLC by a left-shift 2x.
Bit 4 Bit 3
D5 D4 D3
Value
0.0 V
0.04 V
10.0 V
10.2 V
> 10.2 V
2.0 V
2.032 V
10.0 V
10.16 V
> 10.16 V
0.0 mA
0.08 mA
20.0 mA
20.4 mA
> 20.4 mA
4.0 mA
4.064 mA
20.0 mA
20.32 mA
> 20.32 mA
Structure of the I/O Module Data
Bit 2 Bit 1 Bit 0
D2 D1 D0
Example
D0–D7 D0–D7
Decimal Hexadecimal
0 00
1 01
250 FA
255 FF
255 FF
1) 1)
0 00
1 01
250 FA
255 FF
255 FF
0 00
1 01
250 FA
255 FF
255 FF
1) 1)
0 00
1 01
250 FA
255 FF
255 FF
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