Aventics AES Serie Systembeschreibung Seite 109

AVENTICS | AES I/O Modules, Analog | R412018147–BAL–001–AG
6.3.8.2 Process data of the outputs for "13 bits two's complement" data format
The values must be transmitted left justified, i.e. the 12-bit value must be shifted 3 positions to the
left before transmission (multiplication by 8).
The three lowest bits must be set to "0".
Table 59: Structure of the process data of the outputs for "13 bits two's complement" data format
(2AO2M12-E)
Bit Bit Bit Bit
15 14 13 12
D12 D11 D10 D9
D.. : Value of the bit (0/1) *: Unassigned bit, must be set to value "0"
Table 60: Value ranges of the process data of the outputs for "13 bits two's complement" data format
(2AO2M12-E)
Nominal value of the
Resolution
measurement range
0 to 10 V 2.50 mV/bit
0 to 20 mA 5.00 μA/bit
±10 V 2.50 mV/bit
4 to 20 mA 4.00 μA/bit
D.. : Value of the bit (0/1)
Bit Bit Bit Bit Bit
11 10 9 8 7
D8 D7 D6 D5 D4
Value
0 V
2.50 mV
10.0 V
10.2 V
> 10.2 V
0 mA
5.00 μA
20.0 mA
20.4 mA
> 20.4 mA
0 V
2.50 mV
10.0 V
10.2 V
> 10.2 V
-2.50 mV
-10.0 V
-10.2 V
< -10.2 V
4 mA
4.004 mA
20 mA
20.32 mA
> 20.32 mA
Structure of the I/O Module Data
Bit Bit Bit Bit
Bit 2* Bit 1* Bit 0*
6 5 4 3
D3 D2 D1 D0 0
Example
D0–D12 D0–D12
Decimal Hexadecimal
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
-1 1FFF
-4000 1060
-4080 1010
-4096 1000
0 0000
1 0001
4000 FA0
4080 FF0
4095 FFF
109
0 0