Aventics AES Serie Systembeschreibung Seite 90

AVENTICS | AES I/O Modules, Analog | R412018147–BAL–001–AG
90
Structure of the I/O Module Data
6.3.2.2 Process data of the inputs for "13 bits two's complement" data format
The values are transmitted left-justified, i.e. the correct 12-bit values result after the data is shifted
3 positions to the right (division by 8).
Table 20: Structure of the process data of the inputs for "13 bits two's complement" data format (2AI2M12-E)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D12 D11 D10 D9
D.. : Value of the bit (0/1)
Table 21: Value ranges of the process data of the inputs for "13 bits two's complement" data format
(2AI2M12-E)
Nominal value of the
Resolution
measurement range
to
0 10 V 2.50 mV/bit
to
0 20 mA 5.00 μA/bit
±10 V 2.50 mV/bit
±20 mA 5.00 μA/bit
to
2 10 V 2.00 mV/bit
to
4 20 mA 4.00 μA/bit
D.. : Value of the bit (0/1)
1)
In this operating mode, monitoring for a wire break is not possible (see "6.2 Diagnostic data" on page 86).
D8 D7 D6 D5 D4
Value
0 V
2.50 mV
10.0 V
10.2 V
> 10.2 V
0 mA
5.00 μA
20.0 mA
20.4 mA
> 20.4 mA
0 V
2.50 mV
10.0 V
10.2 V
> 10.2 V
-2.50 mV
-10.0 V
-10.2 V
< -10.2 V
0 mA
5.00 μA
20.0 mA
20.4 mA
> 20.4 mA
-5.00 μA
-20.0 mA
-20.4 mA
< -20.4 mA
0 V
2 V
2.002 V
10 V
10.16 V
> 10.16 V
0 mA
4 mA
4.004 mA
20 mA
20.32 mA
> 20.32 mA
D3 D2 D1 D0 0
Example
D0–D12 D0–D12
Decimal Hexadecimal
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
-1 1FFF
-4000 1060
-4080 1010
-4096 1000
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
-1 1FFF
-4000 1060
-4080 1010
-4096 1000
1)
0 000
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
1)
0 000
0 000
1 001
4000 FA0
4080 FF0
4095 FFF
0 0
1)
1)