JVC RX-301BK Serviceanleitung Seite 47
Inhaltsverzeichnis
RX-301BK
RX-301LBK
MLC7218(1C102):
PLL Synthesizer
eo
ee
Se
T
[Symbol
|Pin No. |
Details
|
Function
} 1/0
|
|---—--
|
|
{Xin
|
tL
|
X' tal OSC
|-Crystal
oscillator
(7.2 Miz)
|
1
| Xout
| 24
|
|
|
|
|———_}-—__}
—__f+_—-——"
mam
{|__|
|FM OSC | 19
| Local
oscillator
|-FH OSC is selected
for serial
data
input:
DV-1
is assigned.
|
I
|
|
I
| signal
input
{-Input
frequency
is 10 ~ 130 Miz
(125 mVrms
min.).
|
t
—}———}
———___|—_
<_<
+}
+|
JAM OSC | 18
| Local
oscillator
|-AM OSC is selected, for serial
data
input:
DV-0
is assigned.
{
I
|
|
|
| signal
input
|-When serial
data
is input:
SP=1
is assigned:
|
|
|
|
|
|
-Input
frequency
is 2 ~ 40 MHz
(125 mVrms min.).
|
|
|
|
|*When serial
data
is input:
SP=0 is assigned:
|
|
|
|
|
|
«Input
frequency
is 0.5 ~ 10 MHz
(125 mVrms
min.).
|
|
{ PDI
|
21
|Charge
pump
output{-PLL
charge
pump
output.
0
| PD2
|
22
|
| When
the
local
oscillator
signal
frequency
divided
by N results
|
|
|
|
| in a frequency
higher
than
the reference
frequency,
high
level]
|
|
|
|
| signals
are output
from
PDI
and
PD2.
|
SS
SS
ae
ee
ee
1
|
| SyYC
|
6
| Controller
clock
|-This
is the controller
clock
output
pin and
a 400
kilz signal
0
|
|
|
{ (duty
66 %) is output
after
the power
is turned
ON.
i
|
—_}——----—____
|
| Vdd
|
20
|
Power
supply
|-Power
supply
pin for LC7218.
-
|
|
|
| It supplies
4.5 ~ 6.5
Y¥ when
the
PLL
circuit
is activated.
|
}-——
+—
|__|
|
| Vss
| 23
|
Ground
|-GND pin of LC7218..
-
|
-——_—___+---------_+——_--_
+
|
| cE
|
2
|
Chip enable
|-This pin goes high when serial
data
is input
(DI)
to LC7218 o1|
I
|
|
|
| output from it.
|
|
{
|
ODI
3
Input data
}+Input
pin for serial
data
which
is transmitted
from
the
}
I
|
|
| controller
to LC7218.
|
|
|
}-A total
of 36 bits of data
should
be input
for
initialization.|
|
|
pO
1
5
|
Output
data
|-Output
pin for serial
data
transmitted
from LC7218
to the
}
oO
|
|
|
|
| controller.
|
|
|
|
|
|+A total
of 24 bits can
be output
from
the internal
shift
|
|
|
|
|
| register
in synchronized
with CK.
|
four 0
|
9
|
POWER
|-Latches
OUT 0 ~ OUT 6 of the serial
data
transmitted
from
the|
0
| OUT
| 10
|
asc
| controller,
and inverts
the data
to output
it in parallel.
|
|
}ouT 2
| Ql
|
MONO
{-OUT 0 can outputs
the
time base
for clock
(8 liz).
|
|
{our 3
| «12
=|
FM
| (When TB = 1.)
|
|
Jour 4
| 613
~=«COd
HW
|-OUT 1 and OUT 2 are complementary
outputs.
|
jour 5
| 14—~«O&I
LW
)-OUT 0, OUT 3, OUT "4, OUT 5 and OUT 6 are
N-ch open
drain
|
|
four 6
| 17°
|
IF Reg
| outputs
(up to 13 ¥).
|
|
1 INO
|
7
|
TUNED
|-The data at input ports
IN 0, IN 1 is converted
from paraliel|
I
|
INI
|
8
|
STOP
IN
| to serial,
and can be output
from output
pin DO.
|
|
| ICTR
| 16
[General
purpose
|-With
serial
data
input:
SC = 1, ICTR
is selected.
t
-
|
1(FM
IF) {
|measurement
signal|-The
signal
is transmitted
to the general-purpose
counter
|
|
|
Jinput
pin
| (20-bit
binary counter)
via a 1/8 divider
internally.
|
|
[-————-|
| LCTR
| 15
[General
purpose
|-With serial
data
input:
SC = 9, LCTR
is selected.
|
[CAM
TF)|
|counter
frequency
|-At
this
time,
if serial
data
is input:
SF = 1 ;
|
|
Jinput
pin
|
-The signal
is transmitted
directly
to the general-purpose
|
|
|
|
|
counter without passing
through
the internal
1/8 divider.
|
|
|
|
|-If serial data is input SF = 0 ;
|
|
|
|
|
-Input frequency
is 1 Hz ~ 20kHz
(VIM = 0.7 VDD min.,
|
|
|
|
|
VIL = 0.3 VDD max.)
|
poy es
(lo. 20073) 1-43
Inhaltsverzeichnis
