Inhaltsverzeichnis
Werbung
Verfügbare Sprachen
Verfügbare Sprachen
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2
3
A
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
DSKD
FDCSEL
MINI
DENS
SEPCLK
SEPD
WDOUT
HLT7CLK
CLKOUT
GNO
XTAL.CLKIN
WDIN
EARLY
LATE
HLD
TEST
PO
Pl
P2
Vcc
I/O
I
1
1
1
O
0
DESCRIPTION
This inpul is the raw read dala leceived Irom Iho d'ive (This input is
aclive Iow.)
This mput Signal, when Iow, programs Ihe FDC 9229 B for a 179X lype of
LSI Controller. When FDCSEL is high. Ihe FDC 9229<B is progtammed
(or a 765 (8272) type ol Controller. (See lig. A.)
The slale ol this inpul determmes whelher Ihe FDC 9229 B is confrgured
lo suppor18'' 0! SW lloppy disk drive mteriaces l! is Ltsedin conjunclion
with the DENS inpul to prescale Ihe clock lor the dala separa,or. The
slale of Ihfs inpul also alters ihe CLKOUT frequency. Ihe
prscompensahon value. the head load delay time (when in 179X mode)
and iheHLT.CLK Irequency (when in 765 mode) (Seefiqs. 2, 3. and 4.)
The siate of Ihis inpul determmes whelher Ihe FDC 9229'B is configured
to support Single donsity (FM) or double densily (MFM] floppy disk drive
interfaces 11 isused in conjunetion with Ihe MINI input to prescalo Ihe
clock lor the data sopatator The siale ol Ihis input also allers the
CLKOUT Irequency when in Ihe 765 mode. ISee liqs. 2. 3. and 4.)
A squaie-wave wmdow clock Signal oulpul derived Irom Ihe DSKD mput
This outpul ts Ihe regeneraled dala pulse derived Irom Ihe raw dala inpul
I DSKD). This Signal maybeeilhsr aclive Iow or aclive high as
determined by FDCSEL (pin 2).
0
The precompensaled WRITE DATA siream lo Ihe drive.
0
When in the 765 mode (FDCSEL high). Ihis oulpul is ihe master dock lo
iheNoppy disKconlroller. Wheninthe 179Xmode, Ihis Signal goc-s high
afler Ihe head load de'ay has occufed following Ihe HLD inpul going
high. This ouipulistelriggerable. (Seelrg 3.)
0
This signal is the write clock lo Ihe floppy diskconlroller. Ils frequency is
delerminerj by Ihe slale ol Ihe MINI. DENS. and FDCSEL inpul pms.
ISee lig. 3.)
Ground
1
1
1
1
1
1
1
1
1
Thisinpulisfordireclconnectiontoa16 MHzor8 MHzcryslal. (Tlie
olher pin o( the cryslal is grounded, and a 470k resislor is connecled
acrosslhecrystal.] XTALCLK1N may allernalively beconnected loa
single-phase TTL-Ievei clock.
The wn!e dala siream from ihe floppy disK Controller.
When this input is high, ihe currenl WRITE DATA pulse v/ill be wrüten late
lothedisk.
When Ihis inpul is high, Ihe currenl WRITE DATA pulse will be writlen
early tolhedisk.
When both EARLY and LATE are Iow, ihe current WRITE DATA pulse will
be written at the nominal Position.
This input isonly used in 179Xmode. A high level ai this inpul causes a
high level on the HLT/CLK outpul alter the specified head-load time
delay has elapsed. The delay is selected by the state of Ihe MINI Output.
(Seefig. 3.)
This input (when Iow) decreases Ihe head-load lime delay and initiahzes
the data Separator. This pin istorteslpurposesonly. This input has an
intemal pull-up resislor and should be lied high or disconnecled lor
normal Operation.
P2-P0 select the amounl ol precompensation applied to the wiile data.
(See lig-2.)
► 5VOLTSUPPLY
Werbung
Inhaltsverzeichnis
