Graf Elektronik FLO3 Handbuch Seite 57

CONTROL BYTES FOR INITIALIZATION
DATA PATTERN
IN DR (HEX)
00 thru F4
F5
F6
F7
FB Ihm FB
FC
FD
FE
FF
FD179X INTERPRETATION
IN FM (UUEN = 1)
Write 00 ihm F4 with CLK = FF
Nol Allowed
Not Allowed
Generate 2 CRC byles
Write FB ihru FB, Clk = C7, Preset CRC
Write FC with Clk = D7
Write FD with Clk = FF
Write FE, Clk = C7. Preset CRC
Write FF with Clk = FF
FD1791/3 INTERPRETATION
IN MFM (ÖTJER ■ 0]
Write 00 thru F4, in MFM
Write AT in MFM. Preset CRC
Write C2" in MFM
Generate 2 CRC bytes
Write F8 thru FB. in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
'Missing dock transition belween bils 4 and 5
■'MiBsing dock iransition between üils 3 8 4
WRITE TRACK FORMATTING THE DfSK
(Refar to section on Type IM commands tor ilow diagrams.)
Formatting the disk Is a relatlvely simple task when
operatlng programmed I/O or when operating under DMA
with a iarge amount oi memory. Data and gap information
mu3t be provided at the Computer intertace. Formatting ihe
disk ts accomplished by positlonlng tho R/W head over ihe
desired Irack number and issuing Ihe Write Track com-
mand.
Upon receipt of the Write Track commana, the head is
loaded and the Busy Stalus bil Is set. Writing Starts wilh
the leading edge o( the flrst encounlered Index pulse and
contlnues untll ihe next Index pulse, at which time the
Interrupt Is activated. The Data Requost Is activated im-
medlately upon recelving the command. Out writing will not
alart untll after the lirst byte has been loaded into ihe Daia
Register. If the DR has not been loaded by ihe time the
Index pulse is encountered the Operation is terminated
maklng the device Nol Busy, the Lost Data Status Bit is set.
and 1ha Interrupt is activated. II a byte is not present in the
DR when needed, a byte of zeroes is subsllluled.
Thls sequence coniinues trom one Index mark to the nexl
index mark, Nomially, whateverdala patlern appears in the
data register is wrilten on ihe disk with a normal dock
pattem. However, il the FD179X detects a dala pattern of
F5 Ihru FE in the data register, thls Is Interpreted as data
address marks wilh mlsslng clocks or CRC generation.
The CRC generator Is inlllallzed wlien any data byte (rom
F8 lo FE is aboul lo be transferred from Ihe DR to the DSR
in FM or by receipl of F5 in MFM. An F7 pattem will
ganeraie two CRC characters in FM or MFM. As a con-
sequence, the paltema F5 thru FE must not appear In the
gaps, data flelds, or 1D fields. Also, CRC's must be
generated by an F7 pattern.
Diska may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128,256,512, or 1024 Bytes.
TYPE IV COMMANDS
The Forced Interrupt command is generally used lo 1er-
minate a multiple sector read or wrile command or to in
su re Type I Status in the Status register. This command can
be loaded into ihe command regisier ai any time. II there is
a cunent command under execution (busy slatus bit seil
tho command will be terminated and the busy Status bit
reset.
The tower four bits of the command delormlne Ihe con-
dilional interrupt as follows:
'0 = Noi-Ready loReady Transition
'1 = ReaüytoNot-ReadyTransilion
l2 = Every Index Pulse
b = Immediale Interrupt
The conditionai interrupt is enabled when Ihe cor-
responding bit positions of the command ('3 - '0} are SBt to
a 1. Then, when the condition for interrupt is mot, the IN-
TRO tine will go high signifying that the condllion specified
has occuned. If '3 ■ lo are all set to zero (HEX DO), no in-
terrupt will occur but any command presently under
execution will be immediately lerminated. When using the
immediate interrupt condilion ('3 = 1) an intgraipt will be
immediately generated and the currenl command ter
minated. Readlng the Status or writing to the command
register will nol automatically clear the interrupt. The HEX
DO ts the only command that will enable the immediate
interrupt (HEX D8) to clear on a subsequent load command
regisler or read slatus register Operation. Follow a HEX DS
with DO command.
Wait 8 micro See (double densily) or 16 micro sec (Single
density before issuing a new command alter issuing a
forced Interrupt (times double when dock = 1 MHz).
Loading a new command sooner than Ihis will nullify the
lorced Interrupt.
Forced Interrupt stops any command at the end of an in-
ternal micro-instruetion and generates INTRQ when the
specified condition is met. Forced interrupt will waii until
ALU operations in progress are complete (CRC
calcuiations. compares. etc.).
More than one condition may De set at a time. II for
example, the READY TO NOT-READY condition (M = 1)
and the Every Index Pulse ('2 = 1) are both set, Ihe
resullant command would be HEX "DA". Tho "OR" func>
hon is performed so that either a READY TO NOT- READY
or the next I ndex Pulse will cause an interrupt condition.
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