Graf Elektronik FLO3 Handbuch Seite 48

FD179X BLOCK DiAQRAM
denslty (FM) Is assumed. 1792 & 1794 are Single density
only.
AM Detsctor—The address mark daiector datecta 10, data
and Index address marks during read and write operalions.
PROCESSOR INTERFACE
The Interface to the processor Is accompllshed through the
eight Data Access Lines (BÄH) and assoclated control
Signals. The DAL are used to transfer Data, Status, and
Control words out of, or Into the FD179X. Ths DAL are three
State buffers that are enabl8d_as Output drtvers when Chip
Select (CS) and Read Enable {REJare actlve (tow loglc State)
or act as Input racelvers when CS and Write Enable (WE)
are activa
When transfer of data wlth the Floppy Disk Controller Is
required by the host processor, the device address is
decoded and CS is mada low/Tne address bits A1 and AO,
comblned with tha Signals RE during a Read Operation or
WE during a Write Operation are Interpreted as selectlng
the followlng regfsters:
A1 • AO
READ(RE) WRITE (Wl)
0 0 Status Register Command Register
0 1 Track Register Track Register
1 0 Sector Register Sector Register
1 1 Data Register Data Register
During Dlrect Memory Access (DMA) types of data
transfers between the Data Register of the FD179X and the
processor, the Data Request (DRQ) Output is used In Data
Transfer control. Thls Signal also appeara as Status bit 1
during Read and Write operalions.
On Disk Read operatlons the Data Request Is actlvated (set
high) when an assemblsd serial Input byte Is transferred In
parallel to the Data Register. This blt is clearad when tha
Data Register Is read by the processor. If the Data Register
is read after one or more charactera are lost, by rtavlng new
data transferred into ths reglstsr prlor to processor readout,
the Lost Data blt is set in the Status Register. The Read
Operation contlnues until the end of sector Is reached.
On Disk Write opsratlons the data Requsst is activated
when the Data Register transfers Its contsnts to the Data
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